Lines Matching refs:v4i8

1313 def : BitconvertPat<i32, v4i8, GPR32, DSPR>;
1315 def : BitconvertPat<v4i8, i32, DSPR, GPR32>;
1319 def : DSPPat<(v4i8 (load addr:$a)),
1320              (v4i8 (COPY_TO_REGCLASS (LW addr:$a), DSPR))>;
1323 def : DSPPat<(store (v4i8 DSPR:$val), addr:$a),
1337 def : DSPBinPat<ADDU_QB, v4i8, int_mips_addu_qb>;
1338 def : DSPBinPat<ADDU_QB, v4i8, add>;
1339 def : DSPBinPat<SUBU_QB, v4i8, int_mips_subu_qb>;
1340 def : DSPBinPat<SUBU_QB, v4i8, sub>;
1357 def : DSPShiftPat<SHLL_QB, v4i8, MipsSHLL_DSP, imm>;
1358 def : DSPShiftPat<SHRA_QB, v4i8, MipsSHRA_DSP, imm, HasDSPR2>;
1359 def : DSPShiftPat<SHRL_QB, v4i8, MipsSHRL_DSP, imm>;
1360 def : DSPShiftPat<SHLL_QB, v4i8, int_mips_shll_qb, immZExt3>;
1361 def : DSPShiftPat<SHRA_QB, v4i8, int_mips_shra_qb, immZExt3, HasDSPR2>;
1362 def : DSPShiftPat<SHRL_QB, v4i8, int_mips_shrl_qb, immZExt3>;
1395 def : DSPSetCCPat<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETEQ>;
1396 def : DSPSetCCPat<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETULT>;
1397 def : DSPSetCCPat<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETULE>;
1398 def : DSPSetCCPatInv<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETNE>;
1399 def : DSPSetCCPatInv<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETUGE>;
1400 def : DSPSetCCPatInv<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETUGT>;
1408 def : DSPSelectCCPat<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETEQ>;
1409 def : DSPSelectCCPat<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETULT>;
1410 def : DSPSelectCCPat<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETULE>;
1411 def : DSPSelectCCPatInv<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETNE>;
1412 def : DSPSelectCCPatInv<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETUGE>;
1413 def : DSPSelectCCPatInv<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETUGT>;