Lines Matching refs:RightReg
587 unsigned RightReg = getRegEnsuringSimpleIntegerWidening(Right, IsUnsigned); in emitCmp() local
588 if (RightReg == 0) in emitCmp()
597 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
603 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
608 emitInst(Mips::SLTu, ResultReg).addReg(RightReg).addReg(LeftReg); in emitCmp()
612 emitInst(Mips::SLTu, ResultReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
617 emitInst(Mips::SLTu, TempReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
623 emitInst(Mips::SLTu, TempReg).addReg(RightReg).addReg(LeftReg); in emitCmp()
628 emitInst(Mips::SLT, ResultReg).addReg(RightReg).addReg(LeftReg); in emitCmp()
632 emitInst(Mips::SLT, ResultReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
637 emitInst(Mips::SLT, TempReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
643 emitInst(Mips::SLT, TempReg).addReg(RightReg).addReg(LeftReg); in emitCmp()
692 emitInst(Opc).addReg(LeftReg).addReg(RightReg).addReg( in emitCmp()