Lines Matching refs:emitInst
149 MachineInstrBuilder emitInst(unsigned Opc) { in emitInst() function in __anon9bd1fc840111::MipsFastISel
152 MachineInstrBuilder emitInst(unsigned Opc, unsigned DstReg) { in emitInst() function in __anon9bd1fc840111::MipsFastISel
158 return emitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset); in emitInstStore()
162 return emitInst(Opc, DstReg).addReg(MemReg).addImm(MemOffset); in emitInstLoad()
269 emitInst(Opc, ResultReg).addReg(LHSReg).addReg(RHSReg); in emitLogicalOp()
309 emitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm); in materialize32BitInt()
312 emitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm); in materialize32BitInt()
320 emitInst(Mips::LUi, TmpReg).addImm(Hi); in materialize32BitInt()
321 emitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo); in materialize32BitInt()
323 emitInst(Mips::LUi, ResultReg).addImm(Hi); in materialize32BitInt()
336 emitInst(Mips::MTC1, DestReg).addReg(TempReg); in materializeFP()
344 emitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1); in materializeFP()
361 emitInst(Mips::LW, DestReg) in materializeGV()
367 emitInst(Mips::ADDiu, TempReg) in materializeGV()
378 emitInst(Mips::LW, DestReg) in materializeExternalCallSym()
597 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
598 emitInst(Mips::SLTiu, ResultReg).addReg(TempReg).addImm(1); in emitCmp()
603 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
604 emitInst(Mips::SLTu, ResultReg).addReg(Mips::ZERO).addReg(TempReg); in emitCmp()
608 emitInst(Mips::SLTu, ResultReg).addReg(RightReg).addReg(LeftReg); in emitCmp()
612 emitInst(Mips::SLTu, ResultReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
617 emitInst(Mips::SLTu, TempReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
618 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1); in emitCmp()
623 emitInst(Mips::SLTu, TempReg).addReg(RightReg).addReg(LeftReg); in emitCmp()
624 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1); in emitCmp()
628 emitInst(Mips::SLT, ResultReg).addReg(RightReg).addReg(LeftReg); in emitCmp()
632 emitInst(Mips::SLT, ResultReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
637 emitInst(Mips::SLT, TempReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
638 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1); in emitCmp()
643 emitInst(Mips::SLT, TempReg).addReg(RightReg).addReg(LeftReg); in emitCmp()
644 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1); in emitCmp()
690 emitInst(Mips::ADDiu, RegWithZero).addReg(Mips::ZERO).addImm(0); in emitCmp()
691 emitInst(Mips::ADDiu, RegWithOne).addReg(Mips::ZERO).addImm(1); in emitCmp()
692 emitInst(Opc).addReg(LeftReg).addReg(RightReg).addReg( in emitCmp()
694 MachineInstrBuilder MI = emitInst(CondMovOpc, ResultReg) in emitCmp()
952 emitInst(Mips::CVT_D32_S, DestReg).addReg(SrcReg); in selectFPExt()
1001 emitInst(TargetOpcode::COPY, TempReg).addReg(Src2Reg); in selectSelect()
1002 emitInst(CondMovOpc, ResultReg) in selectSelect()
1027 emitInst(Mips::CVT_S_D32, DestReg).addReg(SrcReg); in selectFPTrunc()
1066 emitInst(Opc, TempReg).addReg(SrcReg); in selectFPToInt()
1067 emitInst(Mips::MFC1, DestReg).addReg(TempReg); in selectFPToInt()
1086 emitInst(Mips::ADJCALLSTACKDOWN).addImm(16); in processCallArgs()
1210 emitInst(Mips::ADJCALLSTACKUP).addImm(16); in finishCall()
1307 emitInst(TargetOpcode::COPY, Mips::T9).addReg(DestAddress); in fastLowerCall()
1348 emitInst(Mips::WSBH, DestReg).addReg(SrcReg); in fastLowerIntrinsicCall()
1358 emitInst(Mips::SLL, TempReg[0]).addReg(SrcReg).addImm(8); in fastLowerIntrinsicCall()
1359 emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(8); in fastLowerIntrinsicCall()
1360 emitInst(Mips::OR, TempReg[2]).addReg(TempReg[0]).addReg(TempReg[1]); in fastLowerIntrinsicCall()
1361 emitInst(Mips::ANDi, DestReg).addReg(TempReg[2]).addImm(0xFFFF); in fastLowerIntrinsicCall()
1368 emitInst(Mips::WSBH, TempReg).addReg(SrcReg); in fastLowerIntrinsicCall()
1369 emitInst(Mips::ROTR, DestReg).addReg(TempReg).addImm(16); in fastLowerIntrinsicCall()
1380 emitInst(Mips::SRL, TempReg[0]).addReg(SrcReg).addImm(8); in fastLowerIntrinsicCall()
1381 emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(24); in fastLowerIntrinsicCall()
1382 emitInst(Mips::ANDi, TempReg[2]).addReg(TempReg[0]).addImm(0xFF00); in fastLowerIntrinsicCall()
1383 emitInst(Mips::OR, TempReg[3]).addReg(TempReg[1]).addReg(TempReg[2]); in fastLowerIntrinsicCall()
1385 emitInst(Mips::ANDi, TempReg[4]).addReg(SrcReg).addImm(0xFF00); in fastLowerIntrinsicCall()
1386 emitInst(Mips::SLL, TempReg[5]).addReg(TempReg[4]).addImm(8); in fastLowerIntrinsicCall()
1388 emitInst(Mips::SLL, TempReg[6]).addReg(SrcReg).addImm(24); in fastLowerIntrinsicCall()
1389 emitInst(Mips::OR, TempReg[7]).addReg(TempReg[3]).addReg(TempReg[5]); in fastLowerIntrinsicCall()
1390 emitInst(Mips::OR, DestReg).addReg(TempReg[6]).addReg(TempReg[7]); in fastLowerIntrinsicCall()
1506 MachineInstrBuilder MIB = emitInst(Mips::RetRA); in selectRet()
1576 emitInst(Mips::SLL, TempReg).addReg(SrcReg).addImm(ShiftAmt); in emitIntSExt32r1()
1577 emitInst(Mips::SRA, DestReg).addReg(TempReg).addImm(ShiftAmt); in emitIntSExt32r1()
1587 emitInst(Mips::SEB, DestReg).addReg(SrcReg); in emitIntSExt32r2()
1590 emitInst(Mips::SEH, DestReg).addReg(SrcReg); in emitIntSExt32r2()
1623 emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(Imm); in emitIntZExt()
1676 emitInst(DivOpc).addReg(Src0Reg).addReg(Src1Reg); in selectDivRem()
1677 emitInst(Mips::TEQ).addReg(Src1Reg).addReg(Mips::ZERO).addImm(7); in selectDivRem()
1686 emitInst(MFOpc, ResultReg); in selectDivRem()
1739 emitInst(Opcode, ResultReg).addReg(Op0Reg).addImm(ShiftVal); in selectShift()
1762 emitInst(Opcode, ResultReg).addReg(Op0Reg).addReg(Op1Reg); in selectShift()
1847 emitInst(Mips::ADDu, DestReg).addReg(TempReg).addReg(Addr.getReg()); in simplifyAddress()