2555   SDValue Wt;  in lowerVECTOR_SHUFFLE_ILVEV()  local
2563     Wt = Op->getOperand(0);  in lowerVECTOR_SHUFFLE_ILVEV()
2565     Wt = Op->getOperand(1);  in lowerVECTOR_SHUFFLE_ILVEV()
2578   return DAG.getNode(MipsISD::ILVEV, SDLoc(Op), ResTy, Ws, Wt);  in lowerVECTOR_SHUFFLE_ILVEV()
2601   SDValue Wt;  in lowerVECTOR_SHUFFLE_ILVOD()  local
2609     Wt = Op->getOperand(0);  in lowerVECTOR_SHUFFLE_ILVOD()
2611     Wt = Op->getOperand(1);  in lowerVECTOR_SHUFFLE_ILVOD()
2624   return DAG.getNode(MipsISD::ILVOD, SDLoc(Op), ResTy, Wt, Ws);  in lowerVECTOR_SHUFFLE_ILVOD()
2648   SDValue Wt;  in lowerVECTOR_SHUFFLE_ILVR()  local
2656     Wt = Op->getOperand(0);  in lowerVECTOR_SHUFFLE_ILVR()
2658     Wt = Op->getOperand(1);  in lowerVECTOR_SHUFFLE_ILVR()
2671   return DAG.getNode(MipsISD::ILVR, SDLoc(Op), ResTy, Ws, Wt);  in lowerVECTOR_SHUFFLE_ILVR()
2696   SDValue Wt;  in lowerVECTOR_SHUFFLE_ILVL()  local
2704     Wt = Op->getOperand(0);  in lowerVECTOR_SHUFFLE_ILVL()
2706     Wt = Op->getOperand(1);  in lowerVECTOR_SHUFFLE_ILVL()
2720   return DAG.getNode(MipsISD::ILVL, SDLoc(Op), ResTy, Ws, Wt);  in lowerVECTOR_SHUFFLE_ILVL()
2743   SDValue Wt;  in lowerVECTOR_SHUFFLE_PCKEV()  local
2750     Wt = Op->getOperand(0);  in lowerVECTOR_SHUFFLE_PCKEV()
2752     Wt = Op->getOperand(1);  in lowerVECTOR_SHUFFLE_PCKEV()
2763   return DAG.getNode(MipsISD::PCKEV, SDLoc(Op), ResTy, Ws, Wt);  in lowerVECTOR_SHUFFLE_PCKEV()
2786   SDValue Wt;  in lowerVECTOR_SHUFFLE_PCKOD()  local
2793     Wt = Op->getOperand(0);  in lowerVECTOR_SHUFFLE_PCKOD()
2795     Wt = Op->getOperand(1);  in lowerVECTOR_SHUFFLE_PCKOD()
2806   return DAG.getNode(MipsISD::PCKOD, SDLoc(Op), ResTy, Ws, Wt);  in lowerVECTOR_SHUFFLE_PCKOD()
3060     unsigned Wt = Ws;  in emitCOPY_FW()  local
3064       Wt = RegInfo.createVirtualRegister(&Mips::MSA128WEvensRegClass);  in emitCOPY_FW()
3066       BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Wt).addReg(Ws);  in emitCOPY_FW()
3069     BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo);  in emitCOPY_FW()
3071     unsigned Wt = RegInfo.createVirtualRegister(  in emitCOPY_FW()  local
3075     BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wt).addReg(Ws).addImm(Lane);  in emitCOPY_FW()
3076     BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo);  in emitCOPY_FW()
3107     unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);  in emitCOPY_FD()  local
3109     BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wt).addReg(Ws).addImm(1);  in emitCOPY_FD()
3110     BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_64);  in emitCOPY_FD()
3133   unsigned Wt = RegInfo.createVirtualRegister(  in emitINSERT_FW()  local
3137   BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)  in emitINSERT_FW()
3144       .addReg(Wt)  in emitINSERT_FW()
3169   unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);  in emitINSERT_FD()  local
3171   BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)  in emitINSERT_FD()
3178       .addReg(Wt)  in emitINSERT_FD()
3254     unsigned Wt = RegInfo.createVirtualRegister(VecRC);  in emitINSERT_DF_VIDX()  local
3255     BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)  in emitINSERT_DF_VIDX()
3259     SrcValReg = Wt;  in emitINSERT_DF_VIDX()