Lines Matching refs:Opc
43 unsigned Opc = MI->getOpcode(); in isLoadFromStackSlot() local
45 if ((Opc == Mips::LW) || (Opc == Mips::LD) || in isLoadFromStackSlot()
46 (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) { in isLoadFromStackSlot()
65 unsigned Opc = MI->getOpcode(); in isStoreToStackSlot() local
67 if ((Opc == Mips::SW) || (Opc == Mips::SD) || in isStoreToStackSlot()
68 (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164)) { in isStoreToStackSlot()
83 unsigned Opc = 0, ZeroReg = 0; in copyPhysReg() local
89 Opc = Mips::MOVE16_MM; in copyPhysReg()
91 Opc = Mips::OR, ZeroReg = Mips::ZERO; in copyPhysReg()
93 Opc = Mips::CFC1; in copyPhysReg()
95 Opc = Mips::MFC1; in copyPhysReg()
97 Opc = isMicroMips ? Mips::MFHI16_MM : Mips::MFHI; in copyPhysReg()
100 Opc = isMicroMips ? Mips::MFLO16_MM : Mips::MFLO; in copyPhysReg()
103 Opc = Mips::MFHI_DSP; in copyPhysReg()
105 Opc = Mips::MFLO_DSP; in copyPhysReg()
112 Opc = Mips::CFCMSA; in copyPhysReg()
116 Opc = Mips::CTC1; in copyPhysReg()
118 Opc = Mips::MTC1; in copyPhysReg()
120 Opc = Mips::MTHI, DestReg = 0; in copyPhysReg()
122 Opc = Mips::MTLO, DestReg = 0; in copyPhysReg()
124 Opc = Mips::MTHI_DSP; in copyPhysReg()
126 Opc = Mips::MTLO_DSP; in copyPhysReg()
134 Opc = Mips::CTCMSA; in copyPhysReg()
137 Opc = Mips::FMOV_S; in copyPhysReg()
139 Opc = Mips::FMOV_D32; in copyPhysReg()
141 Opc = Mips::FMOV_D64; in copyPhysReg()
144 Opc = Mips::OR64, ZeroReg = Mips::ZERO_64; in copyPhysReg()
146 Opc = Mips::MFHI64, SrcReg = 0; in copyPhysReg()
148 Opc = Mips::MFLO64, SrcReg = 0; in copyPhysReg()
150 Opc = Mips::DMFC1; in copyPhysReg()
154 Opc = Mips::MTHI64, DestReg = 0; in copyPhysReg()
156 Opc = Mips::MTLO64, DestReg = 0; in copyPhysReg()
158 Opc = Mips::DMTC1; in copyPhysReg()
162 Opc = Mips::MOVE_V; in copyPhysReg()
165 assert(Opc && "Cannot copy registers"); in copyPhysReg()
167 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc)); in copyPhysReg()
187 unsigned Opc = 0; in storeRegToStack() local
190 Opc = Mips::SW; in storeRegToStack()
192 Opc = Mips::SD; in storeRegToStack()
194 Opc = Mips::STORE_ACC64; in storeRegToStack()
196 Opc = Mips::STORE_ACC64DSP; in storeRegToStack()
198 Opc = Mips::STORE_ACC128; in storeRegToStack()
200 Opc = Mips::STORE_CCOND_DSP; in storeRegToStack()
202 Opc = Mips::SWC1; in storeRegToStack()
204 Opc = Mips::SDC1; in storeRegToStack()
206 Opc = Mips::SDC164; in storeRegToStack()
208 Opc = Mips::ST_B; in storeRegToStack()
210 Opc = Mips::ST_H; in storeRegToStack()
212 Opc = Mips::ST_W; in storeRegToStack()
214 Opc = Mips::ST_D; in storeRegToStack()
216 Opc = Mips::SW; in storeRegToStack()
218 Opc = Mips::SD; in storeRegToStack()
220 Opc = Mips::SW; in storeRegToStack()
222 Opc = Mips::SD; in storeRegToStack()
243 assert(Opc && "Register class not handled!"); in storeRegToStack()
244 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)) in storeRegToStack()
255 unsigned Opc = 0; in loadRegFromStack() local
263 Opc = Mips::LW; in loadRegFromStack()
265 Opc = Mips::LD; in loadRegFromStack()
267 Opc = Mips::LOAD_ACC64; in loadRegFromStack()
269 Opc = Mips::LOAD_ACC64DSP; in loadRegFromStack()
271 Opc = Mips::LOAD_ACC128; in loadRegFromStack()
273 Opc = Mips::LOAD_CCOND_DSP; in loadRegFromStack()
275 Opc = Mips::LWC1; in loadRegFromStack()
277 Opc = Mips::LDC1; in loadRegFromStack()
279 Opc = Mips::LDC164; in loadRegFromStack()
281 Opc = Mips::LD_B; in loadRegFromStack()
283 Opc = Mips::LD_H; in loadRegFromStack()
285 Opc = Mips::LD_W; in loadRegFromStack()
287 Opc = Mips::LD_D; in loadRegFromStack()
289 Opc = Mips::LW; in loadRegFromStack()
291 Opc = Mips::LD; in loadRegFromStack()
293 Opc = Mips::LW; in loadRegFromStack()
295 Opc = Mips::LD; in loadRegFromStack()
297 assert(Opc && "Register class not handled!"); in loadRegFromStack()
300 BuildMI(MBB, I, DL, get(Opc), DestReg) in loadRegFromStack()
320 BuildMI(MBB, I, DL, get(Opc), Reg) in loadRegFromStack()
331 unsigned Opc; in expandPostRAPseudo() local
343 Opc = isMicroMips ? Mips::MFHI16_MM : Mips::MFHI; in expandPostRAPseudo()
344 expandPseudoMFHiLo(MBB, MI, Opc); in expandPostRAPseudo()
347 Opc = isMicroMips ? Mips::MFLO16_MM : Mips::MFLO; in expandPostRAPseudo()
348 expandPseudoMFHiLo(MBB, MI, Opc); in expandPostRAPseudo()
404 unsigned MipsSEInstrInfo::getOppositeBranchOpc(unsigned Opc) const { in getOppositeBranchOpc()
405 switch (Opc) { in getOppositeBranchOpc()
473 if (Inst->Opc == LUi) in loadImmediate()
476 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(ZEROReg) in loadImmediate()
481 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(Reg, RegState::Kill) in loadImmediate()
490 unsigned MipsSEInstrInfo::getAnalyzableBrOpc(unsigned Opc) const { in getAnalyzableBrOpc()
491 return (Opc == Mips::BEQ || Opc == Mips::BNE || Opc == Mips::BGTZ || in getAnalyzableBrOpc()
492 Opc == Mips::BGEZ || Opc == Mips::BLTZ || Opc == Mips::BLEZ || in getAnalyzableBrOpc()
493 Opc == Mips::BEQ64 || Opc == Mips::BNE64 || Opc == Mips::BGTZ64 || in getAnalyzableBrOpc()
494 Opc == Mips::BGEZ64 || Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 || in getAnalyzableBrOpc()
495 Opc == Mips::BC1T || Opc == Mips::BC1F || Opc == Mips::B || in getAnalyzableBrOpc()
496 Opc == Mips::J || Opc == Mips::BEQZC_MM || Opc == Mips::BNEZC_MM) ? in getAnalyzableBrOpc()
497 Opc : 0; in getAnalyzableBrOpc()
515 MipsSEInstrInfo::compareOpndSize(unsigned Opc, in compareOpndSize() argument
517 const MCInstrDesc &Desc = get(Opc); in compareOpndSize()