Lines Matching refs:regclass

1765 class LoadParamMemInst<NVPTXRegClass regclass, string opstr> :
1766       NVPTXInst<(outs regclass:$dst), (ins i32imm:$b),
1771 class LoadParamRegInst<NVPTXRegClass regclass, string opstr> :
1772       NVPTXInst<(outs regclass:$dst), (ins i32imm:$b),
1775                 [(set regclass:$dst, (LoadParam (i32 0), (i32 imm:$b)))]>;
1777 class LoadParamV2MemInst<NVPTXRegClass regclass, string opstr> :
1778       NVPTXInst<(outs regclass:$dst, regclass:$dst2), (ins i32imm:$b),
1782 class LoadParamV4MemInst<NVPTXRegClass regclass, string opstr> :
1783       NVPTXInst<(outs regclass:$dst, regclass:$dst2, regclass:$dst3,
1784                       regclass:$dst4),
1789 class StoreParamInst<NVPTXRegClass regclass, string opstr> :
1790       NVPTXInst<(outs), (ins regclass:$val, i32imm:$a, i32imm:$b),
1795 class StoreParamV2Inst<NVPTXRegClass regclass, string opstr> :
1796       NVPTXInst<(outs), (ins regclass:$val, regclass:$val2,
1802 class StoreParamV4Inst<NVPTXRegClass regclass, string opstr> :
1803       NVPTXInst<(outs), (ins regclass:$val, regclass:$val1, regclass:$val2,
1804                              regclass:$val3, i32imm:$a, i32imm:$b),
1809 class StoreRetvalInst<NVPTXRegClass regclass, string opstr> :
1810       NVPTXInst<(outs), (ins regclass:$val, i32imm:$a),
1815 class StoreRetvalV2Inst<NVPTXRegClass regclass, string opstr> :
1816       NVPTXInst<(outs), (ins regclass:$val, regclass:$val2, i32imm:$a),
1821 class StoreRetvalV4Inst<NVPTXRegClass regclass, string opstr> :
1823                 (ins regclass:$val, regclass:$val2, regclass:$val3,
1824                      regclass:$val4, i32imm:$a),
1971 class CallArgInst<NVPTXRegClass regclass> :
1972       NVPTXInst<(outs), (ins regclass:$a), "$a, ",
1973                 [(CallArg (i32 0), regclass:$a)]>;
1975 class LastCallArgInst<NVPTXRegClass regclass> :
1976       NVPTXInst<(outs), (ins regclass:$a), "$a",
1977                 [(LastCallArg (i32 0), regclass:$a)]>;
2038 class MoveParamInst<NVPTXRegClass regclass, string asmstr> :
2039       NVPTXInst<(outs regclass:$dst), (ins regclass:$src),
2041                 [(set regclass:$dst, (MoveParam regclass:$src))]>;
2051 class PseudoUseParamInst<NVPTXRegClass regclass> :
2052       NVPTXInst<(outs), (ins regclass:$src),
2054       [(PseudoUseParam regclass:$src)]>;
2066 multiclass LD<NVPTXRegClass regclass> {
2067   def _avar : NVPTXInst<(outs regclass:$dst),
2072   def _areg : NVPTXInst<(outs regclass:$dst),
2077   def _areg_64 : NVPTXInst<(outs regclass:$dst),
2082   def _ari : NVPTXInst<(outs regclass:$dst),
2087   def _ari_64 : NVPTXInst<(outs regclass:$dst),
2092   def _asi : NVPTXInst<(outs regclass:$dst),
2108 multiclass ST<NVPTXRegClass regclass> {
2110     (ins regclass:$src, LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec,
2115     (ins regclass:$src, LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec,
2120     (ins regclass:$src, LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec,
2125     (ins regclass:$src, LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec,
2130     (ins regclass:$src, LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec,
2135     (ins regclass:$src, LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec,
2154 multiclass LD_VEC<NVPTXRegClass regclass> {
2155   def _v2_avar : NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
2160   def _v2_areg : NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
2165   def _v2_areg_64 : NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
2170   def _v2_ari : NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
2175   def _v2_ari_64 : NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
2180   def _v2_asi : NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
2185   def _v4_avar : NVPTXInst<(outs regclass:$dst1, regclass:$dst2,
2186       regclass:$dst3, regclass:$dst4),
2191   def _v4_areg : NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
2192       regclass:$dst4),
2197   def _v4_areg_64 : NVPTXInst<(outs regclass:$dst1, regclass:$dst2,
2198                                regclass:$dst3, regclass:$dst4),
2203   def _v4_ari : NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
2204       regclass:$dst4),
2210   def _v4_ari_64 : NVPTXInst<(outs regclass:$dst1, regclass:$dst2,
2211                               regclass:$dst3, regclass:$dst4),
2217   def _v4_asi : NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
2218       regclass:$dst4),
2234 multiclass ST_VEC<NVPTXRegClass regclass> {
2236     (ins regclass:$src1, regclass:$src2, LdStCode:$isVol, LdStCode:$addsp,
2241     (ins regclass:$src1, regclass:$src2, LdStCode:$isVol, LdStCode:$addsp,
2246     (ins regclass:$src1, regclass:$src2, LdStCode:$isVol, LdStCode:$addsp,
2251     (ins regclass:$src1, regclass:$src2, LdStCode:$isVol, LdStCode:$addsp,
2257     (ins regclass:$src1, regclass:$src2, LdStCode:$isVol, LdStCode:$addsp,
2263     (ins regclass:$src1, regclass:$src2, LdStCode:$isVol, LdStCode:$addsp,
2269     (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
2275     (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
2281     (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
2287     (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
2294     (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
2301     (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,