Lines Matching refs:toWidth
2111 LdStCode:$Sign, i32imm:$toWidth, imem:$addr),
2112 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}$toWidth",
2116 LdStCode:$Sign, i32imm:$toWidth, Int32Regs:$addr),
2117 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}$toWidth",
2121 LdStCode:$Sign, i32imm:$toWidth, Int64Regs:$addr),
2122 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}$toWidth ",
2126 LdStCode:$Sign, i32imm:$toWidth, Int32Regs:$addr, i32imm:$offset),
2127 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}$toWidth",
2131 LdStCode:$Sign, i32imm:$toWidth, Int64Regs:$addr, i32imm:$offset),
2132 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}$toWidth ",
2136 LdStCode:$Sign, i32imm:$toWidth, imem:$addr, i32imm:$offset),
2137 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}$toWidth",