Lines Matching refs:Pat

90 def : Pat<(int_nvvm_fmin_f immFloat1,
93 def : Pat<(int_nvvm_fmin_f immFloat1,
96 def : Pat<(int_nvvm_fmin_f
99 def : Pat<(int_nvvm_fmin_f
103 def : Pat<(int_nvvm_fmin_d immDouble1,
106 def : Pat<(int_nvvm_fmin_d immDouble1,
109 def : Pat<(int_nvvm_fmin_d
112 def : Pat<(int_nvvm_fmin_d
302 def : Pat<(int_nvvm_floor_ftz_f Float32Regs:$a),
304 def : Pat<(int_nvvm_floor_f Float32Regs:$a),
306 def : Pat<(int_nvvm_floor_d Float64Regs:$a),
309 def : Pat<(int_nvvm_ceil_ftz_f Float32Regs:$a),
311 def : Pat<(int_nvvm_ceil_f Float32Regs:$a),
313 def : Pat<(int_nvvm_ceil_d Float64Regs:$a),
337 def : Pat<(int_nvvm_round_ftz_f Float32Regs:$a),
339 def : Pat<(int_nvvm_round_f Float32Regs:$a),
341 def : Pat<(int_nvvm_round_d Float64Regs:$a),
348 def : Pat<(int_nvvm_trunc_ftz_f Float32Regs:$a),
350 def : Pat<(int_nvvm_trunc_f Float32Regs:$a),
352 def : Pat<(int_nvvm_trunc_d Float64Regs:$a),
359 def : Pat<(int_nvvm_saturate_ftz_f Float32Regs:$a),
361 def : Pat<(int_nvvm_saturate_f Float32Regs:$a),
363 def : Pat<(int_nvvm_saturate_d Float64Regs:$a),
500 def : Pat<(int_nvvm_sqrt_f Float32Regs:$a),
502 def : Pat<(int_nvvm_sqrt_f Float32Regs:$a),
504 def : Pat<(int_nvvm_sqrt_f Float32Regs:$a),
506 def : Pat<(int_nvvm_sqrt_f Float32Regs:$a),
555 def : Pat<(int_nvvm_d2f_rn_ftz Float64Regs:$a),
557 def : Pat<(int_nvvm_d2f_rn Float64Regs:$a),
559 def : Pat<(int_nvvm_d2f_rz_ftz Float64Regs:$a),
561 def : Pat<(int_nvvm_d2f_rz Float64Regs:$a),
563 def : Pat<(int_nvvm_d2f_rm_ftz Float64Regs:$a),
565 def : Pat<(int_nvvm_d2f_rm Float64Regs:$a),
567 def : Pat<(int_nvvm_d2f_rp_ftz Float64Regs:$a),
569 def : Pat<(int_nvvm_d2f_rp Float64Regs:$a),
572 def : Pat<(int_nvvm_d2i_rn Float64Regs:$a),
574 def : Pat<(int_nvvm_d2i_rz Float64Regs:$a),
576 def : Pat<(int_nvvm_d2i_rm Float64Regs:$a),
578 def : Pat<(int_nvvm_d2i_rp Float64Regs:$a),
581 def : Pat<(int_nvvm_d2ui_rn Float64Regs:$a),
583 def : Pat<(int_nvvm_d2ui_rz Float64Regs:$a),
585 def : Pat<(int_nvvm_d2ui_rm Float64Regs:$a),
587 def : Pat<(int_nvvm_d2ui_rp Float64Regs:$a),
590 def : Pat<(int_nvvm_i2d_rn Int32Regs:$a),
592 def : Pat<(int_nvvm_i2d_rz Int32Regs:$a),
594 def : Pat<(int_nvvm_i2d_rm Int32Regs:$a),
596 def : Pat<(int_nvvm_i2d_rp Int32Regs:$a),
599 def : Pat<(int_nvvm_ui2d_rn Int32Regs:$a),
601 def : Pat<(int_nvvm_ui2d_rz Int32Regs:$a),
603 def : Pat<(int_nvvm_ui2d_rm Int32Regs:$a),
605 def : Pat<(int_nvvm_ui2d_rp Int32Regs:$a),
608 def : Pat<(int_nvvm_f2i_rn_ftz Float32Regs:$a),
610 def : Pat<(int_nvvm_f2i_rn Float32Regs:$a),
612 def : Pat<(int_nvvm_f2i_rz_ftz Float32Regs:$a),
614 def : Pat<(int_nvvm_f2i_rz Float32Regs:$a),
616 def : Pat<(int_nvvm_f2i_rm_ftz Float32Regs:$a),
618 def : Pat<(int_nvvm_f2i_rm Float32Regs:$a),
620 def : Pat<(int_nvvm_f2i_rp_ftz Float32Regs:$a),
622 def : Pat<(int_nvvm_f2i_rp Float32Regs:$a),
625 def : Pat<(int_nvvm_f2ui_rn_ftz Float32Regs:$a),
627 def : Pat<(int_nvvm_f2ui_rn Float32Regs:$a),
629 def : Pat<(int_nvvm_f2ui_rz_ftz Float32Regs:$a),
631 def : Pat<(int_nvvm_f2ui_rz Float32Regs:$a),
633 def : Pat<(int_nvvm_f2ui_rm_ftz Float32Regs:$a),
635 def : Pat<(int_nvvm_f2ui_rm Float32Regs:$a),
637 def : Pat<(int_nvvm_f2ui_rp_ftz Float32Regs:$a),
639 def : Pat<(int_nvvm_f2ui_rp Float32Regs:$a),
642 def : Pat<(int_nvvm_i2f_rn Int32Regs:$a),
644 def : Pat<(int_nvvm_i2f_rz Int32Regs:$a),
646 def : Pat<(int_nvvm_i2f_rm Int32Regs:$a),
648 def : Pat<(int_nvvm_i2f_rp Int32Regs:$a),
651 def : Pat<(int_nvvm_ui2f_rn Int32Regs:$a),
653 def : Pat<(int_nvvm_ui2f_rz Int32Regs:$a),
655 def : Pat<(int_nvvm_ui2f_rm Int32Regs:$a),
657 def : Pat<(int_nvvm_ui2f_rp Int32Regs:$a),
674 def : Pat<(int_nvvm_f2ll_rn_ftz Float32Regs:$a),
676 def : Pat<(int_nvvm_f2ll_rn Float32Regs:$a),
678 def : Pat<(int_nvvm_f2ll_rz_ftz Float32Regs:$a),
680 def : Pat<(int_nvvm_f2ll_rz Float32Regs:$a),
682 def : Pat<(int_nvvm_f2ll_rm_ftz Float32Regs:$a),
684 def : Pat<(int_nvvm_f2ll_rm Float32Regs:$a),
686 def : Pat<(int_nvvm_f2ll_rp_ftz Float32Regs:$a),
688 def : Pat<(int_nvvm_f2ll_rp Float32Regs:$a),
691 def : Pat<(int_nvvm_f2ull_rn_ftz Float32Regs:$a),
693 def : Pat<(int_nvvm_f2ull_rn Float32Regs:$a),
695 def : Pat<(int_nvvm_f2ull_rz_ftz Float32Regs:$a),
697 def : Pat<(int_nvvm_f2ull_rz Float32Regs:$a),
699 def : Pat<(int_nvvm_f2ull_rm_ftz Float32Regs:$a),
701 def : Pat<(int_nvvm_f2ull_rm Float32Regs:$a),
703 def : Pat<(int_nvvm_f2ull_rp_ftz Float32Regs:$a),
705 def : Pat<(int_nvvm_f2ull_rp Float32Regs:$a),
708 def : Pat<(int_nvvm_d2ll_rn Float64Regs:$a),
710 def : Pat<(int_nvvm_d2ll_rz Float64Regs:$a),
712 def : Pat<(int_nvvm_d2ll_rm Float64Regs:$a),
714 def : Pat<(int_nvvm_d2ll_rp Float64Regs:$a),
717 def : Pat<(int_nvvm_d2ull_rn Float64Regs:$a),
719 def : Pat<(int_nvvm_d2ull_rz Float64Regs:$a),
721 def : Pat<(int_nvvm_d2ull_rm Float64Regs:$a),
723 def : Pat<(int_nvvm_d2ull_rp Float64Regs:$a),
726 def : Pat<(int_nvvm_ll2f_rn Int64Regs:$a),
728 def : Pat<(int_nvvm_ll2f_rz Int64Regs:$a),
730 def : Pat<(int_nvvm_ll2f_rm Int64Regs:$a),
732 def : Pat<(int_nvvm_ll2f_rp Int64Regs:$a),
735 def : Pat<(int_nvvm_ull2f_rn Int64Regs:$a),
737 def : Pat<(int_nvvm_ull2f_rz Int64Regs:$a),
739 def : Pat<(int_nvvm_ull2f_rm Int64Regs:$a),
741 def : Pat<(int_nvvm_ull2f_rp Int64Regs:$a),
744 def : Pat<(int_nvvm_ll2d_rn Int64Regs:$a),
746 def : Pat<(int_nvvm_ll2d_rz Int64Regs:$a),
748 def : Pat<(int_nvvm_ll2d_rm Int64Regs:$a),
750 def : Pat<(int_nvvm_ll2d_rp Int64Regs:$a),
753 def : Pat<(int_nvvm_ull2d_rn Int64Regs:$a),
755 def : Pat<(int_nvvm_ull2d_rz Int64Regs:$a),
757 def : Pat<(int_nvvm_ull2d_rm Int64Regs:$a),
759 def : Pat<(int_nvvm_ull2d_rp Int64Regs:$a),
767 //def : Pat<(int_nvvm_f2h_rn_ftz Float32Regs:$a),
769 //def : Pat<(int_nvvm_f2h_rn Float32Regs:$a),
772 //def : Pat<(int_nvvm_h2f Int16Regs:$a),
795 def : Pat<(f32 (f16_to_fp Int16Regs:$a)),
797 def : Pat<(i16 (fp_to_f16 Float32Regs:$a)),
799 def : Pat<(i16 (fp_to_f16 Float32Regs:$a)),
802 def : Pat<(f64 (f16_to_fp Int16Regs:$a)),
804 def : Pat<(i16 (fp_to_f16 Float64Regs:$a)),
1706 def : Pat<(i64 (int_nvvm_ptr_gen_to_local (int_nvvm_ptr_local_to_gen
1709 def : Pat<(i32 (int_nvvm_ptr_gen_to_local (int_nvvm_ptr_local_to_gen
1779 def : Pat<(int_nvvm_read_ptx_sreg_envreg0), (MOV_SPECIAL ENVREG0)>;
1780 def : Pat<(int_nvvm_read_ptx_sreg_envreg1), (MOV_SPECIAL ENVREG1)>;
1781 def : Pat<(int_nvvm_read_ptx_sreg_envreg2), (MOV_SPECIAL ENVREG2)>;
1782 def : Pat<(int_nvvm_read_ptx_sreg_envreg3), (MOV_SPECIAL ENVREG3)>;
1783 def : Pat<(int_nvvm_read_ptx_sreg_envreg4), (MOV_SPECIAL ENVREG4)>;
1784 def : Pat<(int_nvvm_read_ptx_sreg_envreg5), (MOV_SPECIAL ENVREG5)>;
1785 def : Pat<(int_nvvm_read_ptx_sreg_envreg6), (MOV_SPECIAL ENVREG6)>;
1786 def : Pat<(int_nvvm_read_ptx_sreg_envreg7), (MOV_SPECIAL ENVREG7)>;
1787 def : Pat<(int_nvvm_read_ptx_sreg_envreg8), (MOV_SPECIAL ENVREG8)>;
1788 def : Pat<(int_nvvm_read_ptx_sreg_envreg9), (MOV_SPECIAL ENVREG9)>;
1789 def : Pat<(int_nvvm_read_ptx_sreg_envreg10), (MOV_SPECIAL ENVREG10)>;
1790 def : Pat<(int_nvvm_read_ptx_sreg_envreg11), (MOV_SPECIAL ENVREG11)>;
1791 def : Pat<(int_nvvm_read_ptx_sreg_envreg12), (MOV_SPECIAL ENVREG12)>;
1792 def : Pat<(int_nvvm_read_ptx_sreg_envreg13), (MOV_SPECIAL ENVREG13)>;
1793 def : Pat<(int_nvvm_read_ptx_sreg_envreg14), (MOV_SPECIAL ENVREG14)>;
1794 def : Pat<(int_nvvm_read_ptx_sreg_envreg15), (MOV_SPECIAL ENVREG15)>;
1795 def : Pat<(int_nvvm_read_ptx_sreg_envreg16), (MOV_SPECIAL ENVREG16)>;
1796 def : Pat<(int_nvvm_read_ptx_sreg_envreg17), (MOV_SPECIAL ENVREG17)>;
1797 def : Pat<(int_nvvm_read_ptx_sreg_envreg18), (MOV_SPECIAL ENVREG18)>;
1798 def : Pat<(int_nvvm_read_ptx_sreg_envreg19), (MOV_SPECIAL ENVREG19)>;
1799 def : Pat<(int_nvvm_read_ptx_sreg_envreg20), (MOV_SPECIAL ENVREG20)>;
1800 def : Pat<(int_nvvm_read_ptx_sreg_envreg21), (MOV_SPECIAL ENVREG21)>;
1801 def : Pat<(int_nvvm_read_ptx_sreg_envreg22), (MOV_SPECIAL ENVREG22)>;
1802 def : Pat<(int_nvvm_read_ptx_sreg_envreg23), (MOV_SPECIAL ENVREG23)>;
1803 def : Pat<(int_nvvm_read_ptx_sreg_envreg24), (MOV_SPECIAL ENVREG24)>;
1804 def : Pat<(int_nvvm_read_ptx_sreg_envreg25), (MOV_SPECIAL ENVREG25)>;
1805 def : Pat<(int_nvvm_read_ptx_sreg_envreg26), (MOV_SPECIAL ENVREG26)>;
1806 def : Pat<(int_nvvm_read_ptx_sreg_envreg27), (MOV_SPECIAL ENVREG27)>;
1807 def : Pat<(int_nvvm_read_ptx_sreg_envreg28), (MOV_SPECIAL ENVREG28)>;
1808 def : Pat<(int_nvvm_read_ptx_sreg_envreg29), (MOV_SPECIAL ENVREG29)>;
1809 def : Pat<(int_nvvm_read_ptx_sreg_envreg30), (MOV_SPECIAL ENVREG30)>;
1810 def : Pat<(int_nvvm_read_ptx_sreg_envreg31), (MOV_SPECIAL ENVREG31)>;
1831 def : Pat<(int_nvvm_rotate_b32 Int32Regs:$src, (i32 imm:$amt)),
1835 def : Pat<(int_nvvm_rotate_b32 Int32Regs:$src, Int32Regs:$amt),
1859 def : Pat<(int_nvvm_swap_lo_hi_b64 Int64Regs:$src),
1889 def : Pat<(int_nvvm_rotate_b64 Int64Regs:$src, (i32 imm:$amt)),
1897 def : Pat<(int_nvvm_rotate_b64 Int64Regs:$src, Int32Regs:$amt),
1906 def : Pat<(int_nvvm_rotate_right_b64 Int64Regs:$src, (i32 imm:$amt)),
1914 def : Pat<(int_nvvm_rotate_right_b64 Int64Regs:$src, Int32Regs:$amt),
1923 def : Pat<(int_nvvm_rotate_b64 Int64Regs:$src, (i32 imm:$amt)),
1926 def : Pat<(int_nvvm_rotate_b64 Int64Regs:$src, Int32Regs:$amt),
1929 def : Pat<(int_nvvm_rotate_right_b64 Int64Regs:$src, (i32 imm:$amt)),
1932 def : Pat<(int_nvvm_rotate_right_b64 Int64Regs:$src, Int32Regs:$amt),
4285 def : Pat<(int_nvvm_txq_channel_order Int64Regs:$a),
4287 def : Pat<(int_nvvm_txq_channel_data_type Int64Regs:$a),
4289 def : Pat<(int_nvvm_txq_width Int64Regs:$a),
4291 def : Pat<(int_nvvm_txq_height Int64Regs:$a),
4293 def : Pat<(int_nvvm_txq_depth Int64Regs:$a),
4295 def : Pat<(int_nvvm_txq_array_size Int64Regs:$a),
4297 def : Pat<(int_nvvm_txq_num_samples Int64Regs:$a),
4299 def : Pat<(int_nvvm_txq_num_mipmap_levels Int64Regs:$a),
4334 def : Pat<(int_nvvm_suq_channel_order Int64Regs:$a),
4336 def : Pat<(int_nvvm_suq_channel_data_type Int64Regs:$a),
4338 def : Pat<(int_nvvm_suq_width Int64Regs:$a),
4340 def : Pat<(int_nvvm_suq_height Int64Regs:$a),
4342 def : Pat<(int_nvvm_suq_depth Int64Regs:$a),
4344 def : Pat<(int_nvvm_suq_array_size Int64Regs:$a),
5697 def : Pat<(int_nvvm_sust_b_1d_i8_clamp
5701 def : Pat<(int_nvvm_sust_b_1d_i16_clamp
5705 def : Pat<(int_nvvm_sust_b_1d_i32_clamp
5709 def : Pat<(int_nvvm_sust_b_1d_i64_clamp
5713 def : Pat<(int_nvvm_sust_b_1d_v2i8_clamp
5718 def : Pat<(int_nvvm_sust_b_1d_v2i16_clamp
5723 def : Pat<(int_nvvm_sust_b_1d_v2i32_clamp
5728 def : Pat<(int_nvvm_sust_b_1d_v2i64_clamp
5733 def : Pat<(int_nvvm_sust_b_1d_v4i8_clamp
5739 def : Pat<(int_nvvm_sust_b_1d_v4i16_clamp
5745 def : Pat<(int_nvvm_sust_b_1d_v4i32_clamp
5753 def : Pat<(int_nvvm_sust_b_1d_array_i8_clamp
5758 def : Pat<(int_nvvm_sust_b_1d_array_i16_clamp
5763 def : Pat<(int_nvvm_sust_b_1d_array_i32_clamp
5768 def : Pat<(int_nvvm_sust_b_1d_array_i64_clamp
5773 def : Pat<(int_nvvm_sust_b_1d_array_v2i8_clamp
5778 def : Pat<(int_nvvm_sust_b_1d_array_v2i16_clamp
5783 def : Pat<(int_nvvm_sust_b_1d_array_v2i32_clamp
5788 def : Pat<(int_nvvm_sust_b_1d_array_v2i64_clamp
5793 def : Pat<(int_nvvm_sust_b_1d_array_v4i8_clamp
5799 def : Pat<(int_nvvm_sust_b_1d_array_v4i16_clamp
5805 def : Pat<(int_nvvm_sust_b_1d_array_v4i32_clamp
5813 def : Pat<(int_nvvm_sust_b_2d_i8_clamp
5818 def : Pat<(int_nvvm_sust_b_2d_i16_clamp
5823 def : Pat<(int_nvvm_sust_b_2d_i32_clamp
5828 def : Pat<(int_nvvm_sust_b_2d_i64_clamp
5833 def : Pat<(int_nvvm_sust_b_2d_v2i8_clamp
5838 def : Pat<(int_nvvm_sust_b_2d_v2i16_clamp
5843 def : Pat<(int_nvvm_sust_b_2d_v2i32_clamp
5848 def : Pat<(int_nvvm_sust_b_2d_v2i64_clamp
5853 def : Pat<(int_nvvm_sust_b_2d_v4i8_clamp
5859 def : Pat<(int_nvvm_sust_b_2d_v4i16_clamp
5865 def : Pat<(int_nvvm_sust_b_2d_v4i32_clamp
5873 def : Pat<(int_nvvm_sust_b_2d_array_i8_clamp
5879 def : Pat<(int_nvvm_sust_b_2d_array_i16_clamp
5885 def : Pat<(int_nvvm_sust_b_2d_array_i32_clamp
5891 def : Pat<(int_nvvm_sust_b_2d_array_i64_clamp
5897 def : Pat<(int_nvvm_sust_b_2d_array_v2i8_clamp
5904 def : Pat<(int_nvvm_sust_b_2d_array_v2i16_clamp
5911 def : Pat<(int_nvvm_sust_b_2d_array_v2i32_clamp
5917 def : Pat<(int_nvvm_sust_b_2d_array_v2i64_clamp
5923 def : Pat<(int_nvvm_sust_b_2d_array_v4i8_clamp
5930 def : Pat<(int_nvvm_sust_b_2d_array_v4i16_clamp
5937 def : Pat<(int_nvvm_sust_b_2d_array_v4i32_clamp
5946 def : Pat<(int_nvvm_sust_b_3d_i8_clamp
5953 def : Pat<(int_nvvm_sust_b_3d_i16_clamp
5960 def : Pat<(int_nvvm_sust_b_3d_i32_clamp
5967 def : Pat<(int_nvvm_sust_b_3d_i64_clamp
5974 def : Pat<(int_nvvm_sust_b_3d_v2i8_clamp
5981 def : Pat<(int_nvvm_sust_b_3d_v2i16_clamp
5988 def : Pat<(int_nvvm_sust_b_3d_v2i32_clamp
5995 def : Pat<(int_nvvm_sust_b_3d_v2i64_clamp
6002 def : Pat<(int_nvvm_sust_b_3d_v4i8_clamp
6009 def : Pat<(int_nvvm_sust_b_3d_v4i16_clamp
6016 def : Pat<(int_nvvm_sust_b_3d_v4i32_clamp
6025 def : Pat<(int_nvvm_sust_b_1d_i8_trap
6029 def : Pat<(int_nvvm_sust_b_1d_i16_trap
6033 def : Pat<(int_nvvm_sust_b_1d_i32_trap
6037 def : Pat<(int_nvvm_sust_b_1d_i64_trap
6041 def : Pat<(int_nvvm_sust_b_1d_v2i8_trap
6046 def : Pat<(int_nvvm_sust_b_1d_v2i16_trap
6051 def : Pat<(int_nvvm_sust_b_1d_v2i32_trap
6056 def : Pat<(int_nvvm_sust_b_1d_v2i64_trap
6061 def : Pat<(int_nvvm_sust_b_1d_v4i8_trap
6067 def : Pat<(int_nvvm_sust_b_1d_v4i16_trap
6073 def : Pat<(int_nvvm_sust_b_1d_v4i32_trap
6081 def : Pat<(int_nvvm_sust_b_1d_array_i8_trap
6086 def : Pat<(int_nvvm_sust_b_1d_array_i16_trap
6091 def : Pat<(int_nvvm_sust_b_1d_array_i32_trap
6096 def : Pat<(int_nvvm_sust_b_1d_array_i64_trap
6101 def : Pat<(int_nvvm_sust_b_1d_array_v2i8_trap
6106 def : Pat<(int_nvvm_sust_b_1d_array_v2i16_trap
6111 def : Pat<(int_nvvm_sust_b_1d_array_v2i32_trap
6116 def : Pat<(int_nvvm_sust_b_1d_array_v2i64_trap
6121 def : Pat<(int_nvvm_sust_b_1d_array_v4i8_trap
6127 def : Pat<(int_nvvm_sust_b_1d_array_v4i16_trap
6133 def : Pat<(int_nvvm_sust_b_1d_array_v4i32_trap
6141 def : Pat<(int_nvvm_sust_b_2d_i8_trap
6146 def : Pat<(int_nvvm_sust_b_2d_i16_trap
6151 def : Pat<(int_nvvm_sust_b_2d_i32_trap
6156 def : Pat<(int_nvvm_sust_b_2d_i64_trap
6161 def : Pat<(int_nvvm_sust_b_2d_v2i8_trap
6166 def : Pat<(int_nvvm_sust_b_2d_v2i16_trap
6171 def : Pat<(int_nvvm_sust_b_2d_v2i32_trap
6176 def : Pat<(int_nvvm_sust_b_2d_v2i64_trap
6181 def : Pat<(int_nvvm_sust_b_2d_v4i8_trap
6187 def : Pat<(int_nvvm_sust_b_2d_v4i16_trap
6193 def : Pat<(int_nvvm_sust_b_2d_v4i32_trap
6201 def : Pat<(int_nvvm_sust_b_2d_array_i8_trap
6207 def : Pat<(int_nvvm_sust_b_2d_array_i16_trap
6213 def : Pat<(int_nvvm_sust_b_2d_array_i32_trap
6219 def : Pat<(int_nvvm_sust_b_2d_array_i64_trap
6225 def : Pat<(int_nvvm_sust_b_2d_array_v2i8_trap
6232 def : Pat<(int_nvvm_sust_b_2d_array_v2i16_trap
6239 def : Pat<(int_nvvm_sust_b_2d_array_v2i32_trap
6245 def : Pat<(int_nvvm_sust_b_2d_array_v2i64_trap
6251 def : Pat<(int_nvvm_sust_b_2d_array_v4i8_trap
6258 def : Pat<(int_nvvm_sust_b_2d_array_v4i16_trap
6265 def : Pat<(int_nvvm_sust_b_2d_array_v4i32_trap
6274 def : Pat<(int_nvvm_sust_b_3d_i8_trap
6281 def : Pat<(int_nvvm_sust_b_3d_i16_trap
6288 def : Pat<(int_nvvm_sust_b_3d_i32_trap
6295 def : Pat<(int_nvvm_sust_b_3d_i64_trap
6302 def : Pat<(int_nvvm_sust_b_3d_v2i8_trap
6309 def : Pat<(int_nvvm_sust_b_3d_v2i16_trap
6316 def : Pat<(int_nvvm_sust_b_3d_v2i32_trap
6323 def : Pat<(int_nvvm_sust_b_3d_v2i64_trap
6330 def : Pat<(int_nvvm_sust_b_3d_v4i8_trap
6337 def : Pat<(int_nvvm_sust_b_3d_v4i16_trap
6344 def : Pat<(int_nvvm_sust_b_3d_v4i32_trap
6353 def : Pat<(int_nvvm_sust_b_1d_i8_zero
6357 def : Pat<(int_nvvm_sust_b_1d_i16_zero
6361 def : Pat<(int_nvvm_sust_b_1d_i32_zero
6365 def : Pat<(int_nvvm_sust_b_1d_i64_zero
6369 def : Pat<(int_nvvm_sust_b_1d_v2i8_zero
6374 def : Pat<(int_nvvm_sust_b_1d_v2i16_zero
6379 def : Pat<(int_nvvm_sust_b_1d_v2i32_zero
6384 def : Pat<(int_nvvm_sust_b_1d_v2i64_zero
6389 def : Pat<(int_nvvm_sust_b_1d_v4i8_zero
6395 def : Pat<(int_nvvm_sust_b_1d_v4i16_zero
6401 def : Pat<(int_nvvm_sust_b_1d_v4i32_zero
6409 def : Pat<(int_nvvm_sust_b_1d_array_i8_zero
6414 def : Pat<(int_nvvm_sust_b_1d_array_i16_zero
6419 def : Pat<(int_nvvm_sust_b_1d_array_i32_zero
6424 def : Pat<(int_nvvm_sust_b_1d_array_i64_zero
6429 def : Pat<(int_nvvm_sust_b_1d_array_v2i8_zero
6434 def : Pat<(int_nvvm_sust_b_1d_array_v2i16_zero
6439 def : Pat<(int_nvvm_sust_b_1d_array_v2i32_zero
6444 def : Pat<(int_nvvm_sust_b_1d_array_v2i64_zero
6449 def : Pat<(int_nvvm_sust_b_1d_array_v4i8_zero
6455 def : Pat<(int_nvvm_sust_b_1d_array_v4i16_zero
6461 def : Pat<(int_nvvm_sust_b_1d_array_v4i32_zero
6469 def : Pat<(int_nvvm_sust_b_2d_i8_zero
6474 def : Pat<(int_nvvm_sust_b_2d_i16_zero
6479 def : Pat<(int_nvvm_sust_b_2d_i32_zero
6484 def : Pat<(int_nvvm_sust_b_2d_i64_zero
6489 def : Pat<(int_nvvm_sust_b_2d_v2i8_zero
6494 def : Pat<(int_nvvm_sust_b_2d_v2i16_zero
6499 def : Pat<(int_nvvm_sust_b_2d_v2i32_zero
6504 def : Pat<(int_nvvm_sust_b_2d_v2i64_zero
6509 def : Pat<(int_nvvm_sust_b_2d_v4i8_zero
6515 def : Pat<(int_nvvm_sust_b_2d_v4i16_zero
6521 def : Pat<(int_nvvm_sust_b_2d_v4i32_zero
6529 def : Pat<(int_nvvm_sust_b_2d_array_i8_zero
6535 def : Pat<(int_nvvm_sust_b_2d_array_i16_zero
6541 def : Pat<(int_nvvm_sust_b_2d_array_i32_zero
6547 def : Pat<(int_nvvm_sust_b_2d_array_i64_zero
6553 def : Pat<(int_nvvm_sust_b_2d_array_v2i8_zero
6560 def : Pat<(int_nvvm_sust_b_2d_array_v2i16_zero
6567 def : Pat<(int_nvvm_sust_b_2d_array_v2i32_zero
6573 def : Pat<(int_nvvm_sust_b_2d_array_v2i64_zero
6579 def : Pat<(int_nvvm_sust_b_2d_array_v4i8_zero
6586 def : Pat<(int_nvvm_sust_b_2d_array_v4i16_zero
6593 def : Pat<(int_nvvm_sust_b_2d_array_v4i32_zero
6602 def : Pat<(int_nvvm_sust_b_3d_i8_zero
6609 def : Pat<(int_nvvm_sust_b_3d_i16_zero
6616 def : Pat<(int_nvvm_sust_b_3d_i32_zero
6623 def : Pat<(int_nvvm_sust_b_3d_i64_zero
6630 def : Pat<(int_nvvm_sust_b_3d_v2i8_zero
6637 def : Pat<(int_nvvm_sust_b_3d_v2i16_zero
6644 def : Pat<(int_nvvm_sust_b_3d_v2i32_zero
6651 def : Pat<(int_nvvm_sust_b_3d_v2i64_zero
6658 def : Pat<(int_nvvm_sust_b_3d_v4i8_zero
6665 def : Pat<(int_nvvm_sust_b_3d_v4i16_zero
6672 def : Pat<(int_nvvm_sust_b_3d_v4i32_zero
6682 def : Pat<(int_nvvm_sust_p_1d_i8_trap
6686 def : Pat<(int_nvvm_sust_p_1d_i16_trap
6690 def : Pat<(int_nvvm_sust_p_1d_i32_trap
6694 def : Pat<(int_nvvm_sust_p_1d_v2i8_trap
6699 def : Pat<(int_nvvm_sust_p_1d_v2i16_trap
6704 def : Pat<(int_nvvm_sust_p_1d_v2i32_trap
6709 def : Pat<(int_nvvm_sust_p_1d_v4i8_trap
6715 def : Pat<(int_nvvm_sust_p_1d_v4i16_trap
6721 def : Pat<(int_nvvm_sust_p_1d_v4i32_trap
6729 def : Pat<(int_nvvm_sust_p_1d_array_i8_trap
6734 def : Pat<(int_nvvm_sust_p_1d_array_i16_trap
6739 def : Pat<(int_nvvm_sust_p_1d_array_i32_trap
6744 def : Pat<(int_nvvm_sust_p_1d_array_v2i8_trap
6749 def : Pat<(int_nvvm_sust_p_1d_array_v2i16_trap
6754 def : Pat<(int_nvvm_sust_p_1d_array_v2i32_trap
6759 def : Pat<(int_nvvm_sust_p_1d_array_v4i8_trap
6765 def : Pat<(int_nvvm_sust_p_1d_array_v4i16_trap
6771 def : Pat<(int_nvvm_sust_p_1d_array_v4i32_trap
6779 def : Pat<(int_nvvm_sust_p_2d_i8_trap
6784 def : Pat<(int_nvvm_sust_p_2d_i16_trap
6789 def : Pat<(int_nvvm_sust_p_2d_i32_trap
6794 def : Pat<(int_nvvm_sust_p_2d_v2i8_trap
6799 def : Pat<(int_nvvm_sust_p_2d_v2i16_trap
6804 def : Pat<(int_nvvm_sust_p_2d_v2i32_trap
6809 def : Pat<(int_nvvm_sust_p_2d_v4i8_trap
6815 def : Pat<(int_nvvm_sust_p_2d_v4i16_trap
6821 def : Pat<(int_nvvm_sust_p_2d_v4i32_trap
6829 def : Pat<(int_nvvm_sust_p_2d_array_i8_trap
6835 def : Pat<(int_nvvm_sust_p_2d_array_i16_trap
6841 def : Pat<(int_nvvm_sust_p_2d_array_i32_trap
6847 def : Pat<(int_nvvm_sust_p_2d_array_v2i8_trap
6854 def : Pat<(int_nvvm_sust_p_2d_array_v2i16_trap
6861 def : Pat<(int_nvvm_sust_p_2d_array_v2i32_trap
6867 def : Pat<(int_nvvm_sust_p_2d_array_v4i8_trap
6874 def : Pat<(int_nvvm_sust_p_2d_array_v4i16_trap
6881 def : Pat<(int_nvvm_sust_p_2d_array_v4i32_trap
6890 def : Pat<(int_nvvm_sust_p_3d_i8_trap
6897 def : Pat<(int_nvvm_sust_p_3d_i16_trap
6904 def : Pat<(int_nvvm_sust_p_3d_i32_trap
6911 def : Pat<(int_nvvm_sust_p_3d_v2i8_trap
6918 def : Pat<(int_nvvm_sust_p_3d_v2i16_trap
6925 def : Pat<(int_nvvm_sust_p_3d_v2i32_trap
6932 def : Pat<(int_nvvm_sust_p_3d_v4i8_trap
6939 def : Pat<(int_nvvm_sust_p_3d_v4i16_trap
6946 def : Pat<(int_nvvm_sust_p_3d_v4i32_trap