Lines Matching refs:regclass
838 multiclass F_ATOMIC_2_imp<NVPTXRegClass ptrclass, NVPTXRegClass regclass,
841 def reg : NVPTXInst<(outs regclass:$dst), (ins ptrclass:$addr, regclass:$b),
847 [(set regclass:$dst, (IntOp ptrclass:$addr, regclass:$b))]>,
849 def imm : NVPTXInst<(outs regclass:$dst), (ins ptrclass:$addr, IMMType:$b),
855 [(set regclass:$dst, (IntOp ptrclass:$addr, IMM:$b))]>,
858 multiclass F_ATOMIC_2<NVPTXRegClass regclass, string SpaceStr, string TypeStr,
860 defm p32 : F_ATOMIC_2_imp<Int32Regs, regclass, SpaceStr, TypeStr, OpcStr,
862 defm p64 : F_ATOMIC_2_imp<Int64Regs, regclass, SpaceStr, TypeStr, OpcStr,
867 multiclass F_ATOMIC_2_NEG_imp<NVPTXRegClass ptrclass, NVPTXRegClass regclass,
870 def reg : NVPTXInst<(outs regclass:$dst), (ins ptrclass:$addr, regclass:$b),
885 [(set regclass:$dst, (IntOp ptrclass:$addr, regclass:$b))]>,
888 multiclass F_ATOMIC_2_NEG<NVPTXRegClass regclass, string SpaceStr,
891 defm p32: F_ATOMIC_2_NEG_imp<Int32Regs, regclass, SpaceStr, TypeStr, OpcStr,
893 defm p64: F_ATOMIC_2_NEG_imp<Int64Regs, regclass, SpaceStr, TypeStr, OpcStr,
898 multiclass F_ATOMIC_3_imp<NVPTXRegClass ptrclass, NVPTXRegClass regclass,
901 def reg : NVPTXInst<(outs regclass:$dst),
902 (ins ptrclass:$addr, regclass:$b, regclass:$c),
908 [(set regclass:$dst,
909 (IntOp ptrclass:$addr, regclass:$b, regclass:$c))]>,
911 def imm1 : NVPTXInst<(outs regclass:$dst),
912 (ins ptrclass:$addr, IMMType:$b, regclass:$c),
918 [(set regclass:$dst, (IntOp ptrclass:$addr, imm:$b, regclass:$c))]>,
920 def imm2 : NVPTXInst<(outs regclass:$dst),
921 (ins ptrclass:$addr, regclass:$b, IMMType:$c),
927 [(set regclass:$dst, (IntOp ptrclass:$addr, regclass:$b, imm:$c))]>,
929 def imm3 : NVPTXInst<(outs regclass:$dst),
936 [(set regclass:$dst, (IntOp ptrclass:$addr, imm:$b, imm:$c))]>,
939 multiclass F_ATOMIC_3<NVPTXRegClass regclass, string SpaceStr, string TypeStr,
941 defm p32 : F_ATOMIC_3_imp<Int32Regs, regclass, SpaceStr, TypeStr, OpcStr,
943 defm p64 : F_ATOMIC_3_imp<Int64Regs, regclass, SpaceStr, TypeStr, OpcStr,
1383 multiclass LDU_G<string TyStr, NVPTXRegClass regclass> {
1384 def areg: NVPTXInst<(outs regclass:$result), (ins Int32Regs:$src),
1387 def areg64: NVPTXInst<(outs regclass:$result), (ins Int64Regs:$src),
1390 def avar: NVPTXInst<(outs regclass:$result), (ins imemAny:$src),
1393 def ari : NVPTXInst<(outs regclass:$result), (ins MEMri:$src),
1396 def ari64 : NVPTXInst<(outs regclass:$result), (ins MEMri64:$src),
1413 multiclass VLDU_G_ELE_V2<string TyStr, NVPTXRegClass regclass> {
1414 def _areg32: NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
1417 def _areg64: NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
1420 def _ari32: NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
1423 def _ari64: NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
1426 def _avar: NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
1431 multiclass VLDU_G_ELE_V4<string TyStr, NVPTXRegClass regclass> {
1432 def _areg32: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
1433 regclass:$dst4), (ins Int32Regs:$src),
1435 def _areg64: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
1436 regclass:$dst4), (ins Int64Regs:$src),
1438 def _ari32: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
1439 regclass:$dst4), (ins MEMri:$src),
1441 def _ari64: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
1442 regclass:$dst4), (ins MEMri64:$src),
1444 def _avar: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
1445 regclass:$dst4), (ins imemAny:$src),
1478 multiclass LDG_G<string TyStr, NVPTXRegClass regclass> {
1479 def areg: NVPTXInst<(outs regclass:$result), (ins Int32Regs:$src),
1482 def areg64: NVPTXInst<(outs regclass:$result), (ins Int64Regs:$src),
1485 def avar: NVPTXInst<(outs regclass:$result), (ins imemAny:$src),
1488 def ari : NVPTXInst<(outs regclass:$result), (ins MEMri:$src),
1491 def ari64 : NVPTXInst<(outs regclass:$result), (ins MEMri64:$src),
1516 multiclass VLDG_G_ELE_V2<string TyStr, NVPTXRegClass regclass> {
1517 def _areg32: NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
1520 def _areg64: NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
1523 def _ari32: NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
1526 def _ari64: NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
1529 def _avar: NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
1534 multiclass VLDG_G_ELE_V4<string TyStr, NVPTXRegClass regclass> {
1535 def _areg32: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
1536 regclass:$dst4), (ins Int32Regs:$src),
1538 def _areg64: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
1539 regclass:$dst4), (ins Int64Regs:$src),
1541 def _ari32: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
1542 regclass:$dst4), (ins MEMri:$src),
1544 def _ari64: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
1545 regclass:$dst4), (ins MEMri64:$src),
1547 def _avar: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
1548 regclass:$dst4), (ins imemAny:$src),