Lines Matching refs:asmstr

18 class NVPTXVecInst<dag outs, dag ins, string asmstr, list<dag> pattern,
20   : NVPTXInst<outs, ins, asmstr, pattern> {
239 class VecBinaryOp<BinOpAsmString asmstr, SDNode OpNode, NVPTXRegClass regclass,
242                  asmstr.s,
246 class VecShiftOp<BinOpAsmString asmstr, SDNode OpNode, NVPTXRegClass regclass1,
249                  asmstr.s,
253 class VecUnaryOp<BinOpAsmString asmstr, PatFrag OpNode, NVPTXRegClass regclass,
256                  asmstr.s,
259 multiclass IntBinVOp<string asmstr, SDNode OpNode,
262   def V2I64 : VecBinaryOp<V2AsmStr<!strconcat(asmstr, "64")>, OpNode, V2I64Regs,
264   def V4I32 : VecBinaryOp<V4AsmStr<!strconcat(asmstr, "32")>, OpNode, V4I32Regs,
266   def V2I32 : VecBinaryOp<V2AsmStr<!strconcat(asmstr, "32")>, OpNode, V2I32Regs,
268   def V4I16 : VecBinaryOp<V4AsmStr<!strconcat(asmstr, "16")>, OpNode, V4I16Regs,
270   def V2I16 : VecBinaryOp<V2AsmStr<!strconcat(asmstr, "16")>, OpNode, V2I16Regs,
272   def V4I8 : VecBinaryOp<V4AsmStr<!strconcat(asmstr, "16")>, OpNode, V4I8Regs,
274   def V2I8 : VecBinaryOp<V2AsmStr<!strconcat(asmstr, "16")>, OpNode, V2I8Regs,
278 multiclass FloatBinVOp<string asmstr, SDNode OpNode,
281   def V2F64 : VecBinaryOp<V2AsmStr<!strconcat(asmstr, "f64")>, OpNode,
283   def V4F32_ftz : VecBinaryOp<V4AsmStr<!strconcat(asmstr, "ftz.f32")>, OpNode,
285   def V2F32_ftz : VecBinaryOp<V2AsmStr<!strconcat(asmstr, "ftz.f32")>, OpNode,
287   def V4F32 : VecBinaryOp<V4AsmStr<!strconcat(asmstr, "f32")>, OpNode,
289   def V2F32 : VecBinaryOp<V2AsmStr<!strconcat(asmstr, "f32")>, OpNode,
293 multiclass IntUnaryVOp<string asmstr, PatFrag OpNode,
296   def V2I64 : VecUnaryOp<V2UnaryStr<!strconcat(asmstr, "64")>, OpNode,
298   def V4I32 : VecUnaryOp<V4UnaryStr<!strconcat(asmstr, "32")>, OpNode,
300   def V2I32 : VecUnaryOp<V2UnaryStr<!strconcat(asmstr, "32")>, OpNode,
302   def V4I16 : VecUnaryOp<V4UnaryStr<!strconcat(asmstr, "16")>, OpNode,
304   def V2I16 : VecUnaryOp<V2UnaryStr<!strconcat(asmstr, "16")>, OpNode,
306   def V4I8  : VecUnaryOp<V4UnaryStr<!strconcat(asmstr, "16")>, OpNode,
308   def V2I8  : VecUnaryOp<V2UnaryStr<!strconcat(asmstr, "16")>, OpNode,
352 class CVTtoVeci32<NVPTXRegClass inclass, NVPTXRegClass outclass, string asmstr,
354       NVPTXVecInst<(outs outclass:$d), (ins inclass:$s), asmstr, [], sInst>;
473 multiclass VMAD<string asmstr, NVPTXRegClass regclassv4,
479                       V4MADStr<asmstr>.s,
486                       V2MADStr<asmstr>.s,
493 multiclass VMADV2Only<string asmstr, NVPTXRegClass regclass, NVPTXInst sop=NOP,
497                       V2MADStr<asmstr>.s,
502 multiclass VFMADV2Only<string asmstr, NVPTXRegClass regclass, NVPTXInst sop=NOP,
506                       V2MADStr<asmstr>.s,
801 class Build_Vector2<string asmstr, NVPTXRegClass vclass, NVPTXRegClass sclass,
805                    !strconcat(asmstr, "\t${dst:vecfull}, {{$a1, $a2}};"),
808 class Build_Vector4<string asmstr, NVPTXRegClass vclass, NVPTXRegClass sclass,
812                !strconcat(asmstr, "\t${dst:vecfull}, {{$a1, $a2, $a3, $a4}};"),
843 class Vec_Move<string asmstr, NVPTXRegClass vclass, NVPTXInst sop=NOP>
845                    !strconcat(asmstr, "\t${dst:vecfull}, ${src:vecfull};"),
924 class Vec_Select<NVPTXRegClass vclass, string asmstr, NVPTXInst sop>
927                      asmstr,