Lines Matching refs:IsZExt
157 const TargetRegisterClass *RC, bool IsZExt = true,
164 unsigned DestReg, bool IsZExt);
451 bool IsZExt, unsigned FP64LoadOpc) { in PPCEmitLoad() argument
479 Opc = (IsZExt ? in PPCEmitLoad()
484 Opc = (IsZExt ? in PPCEmitLoad()
801 bool IsZExt, unsigned DestReg) { in PPCEmitCmp() argument
824 Imm = (IsZExt) ? (long)CIVal.getZExtValue() : (long)CIVal.getSExtValue(); in PPCEmitCmp()
825 if ((IsZExt && isUInt<16>(Imm)) || (!IsZExt && isInt<16>(Imm))) in PPCEmitCmp()
847 CmpOpc = IsZExt ? PPC::CMPLW : PPC::CMPW; in PPCEmitCmp()
849 CmpOpc = IsZExt ? PPC::CMPLWI : PPC::CMPWI; in PPCEmitCmp()
853 CmpOpc = IsZExt ? PPC::CMPLD : PPC::CMPD; in PPCEmitCmp()
855 CmpOpc = IsZExt ? PPC::CMPLDI : PPC::CMPDI; in PPCEmitCmp()
872 if (!PPCEmitIntExt(SrcVT, SrcReg1, MVT::i32, ExtReg, IsZExt)) in PPCEmitCmp()
878 if (!PPCEmitIntExt(SrcVT, SrcReg2, MVT::i32, ExtReg, IsZExt)) in PPCEmitCmp()
1700 unsigned DestReg, bool IsZExt) { in PPCEmitIntExt() argument
1707 if (!IsZExt) { in PPCEmitIntExt()
1802 bool IsZExt = isa<ZExtInst>(I); in SelectIntExt() local
1828 if (!PPCEmitIntExt(SrcVT, SrcReg, DestVT, ResultReg, IsZExt)) in SelectIntExt()
2181 bool IsZExt = false; in tryToFoldLoadIntoMI() local
2188 IsZExt = true; in tryToFoldLoadIntoMI()
2199 IsZExt = true; in tryToFoldLoadIntoMI()
2236 if (!PPCEmitLoad(VT, ResultReg, Addr, nullptr, IsZExt)) in tryToFoldLoadIntoMI()