Lines Matching refs:MVT
70 addRegisterClass(MVT::i32, &PPC::GPRCRegClass); in PPCTargetLowering()
72 addRegisterClass(MVT::f32, &PPC::F4RCRegClass); in PPCTargetLowering()
73 addRegisterClass(MVT::f64, &PPC::F8RCRegClass); in PPCTargetLowering()
77 for (MVT VT : MVT::integer_valuetypes()) { in PPCTargetLowering()
78 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in PPCTargetLowering()
79 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand); in PPCTargetLowering()
82 setTruncStoreAction(MVT::f64, MVT::f32, Expand); in PPCTargetLowering()
85 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal); in PPCTargetLowering()
86 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal); in PPCTargetLowering()
87 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal); in PPCTargetLowering()
88 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal); in PPCTargetLowering()
89 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal); in PPCTargetLowering()
90 setIndexedLoadAction(ISD::PRE_INC, MVT::f32, Legal); in PPCTargetLowering()
91 setIndexedLoadAction(ISD::PRE_INC, MVT::f64, Legal); in PPCTargetLowering()
92 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal); in PPCTargetLowering()
93 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal); in PPCTargetLowering()
94 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal); in PPCTargetLowering()
95 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal); in PPCTargetLowering()
96 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal); in PPCTargetLowering()
97 setIndexedStoreAction(ISD::PRE_INC, MVT::f32, Legal); in PPCTargetLowering()
98 setIndexedStoreAction(ISD::PRE_INC, MVT::f64, Legal); in PPCTargetLowering()
101 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in PPCTargetLowering()
104 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote); in PPCTargetLowering()
105 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1, in PPCTargetLowering()
106 isPPC64 ? MVT::i64 : MVT::i32); in PPCTargetLowering()
107 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote); in PPCTargetLowering()
108 AddPromotedToType(ISD::UINT_TO_FP, MVT::i1, in PPCTargetLowering()
109 isPPC64 ? MVT::i64 : MVT::i32); in PPCTargetLowering()
111 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom); in PPCTargetLowering()
112 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom); in PPCTargetLowering()
116 setOperationAction(ISD::LOAD, MVT::i1, Custom); in PPCTargetLowering()
117 setOperationAction(ISD::STORE, MVT::i1, Custom); in PPCTargetLowering()
121 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom); in PPCTargetLowering()
123 for (MVT VT : MVT::integer_valuetypes()) { in PPCTargetLowering()
124 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in PPCTargetLowering()
125 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in PPCTargetLowering()
126 setTruncStoreAction(VT, MVT::i1, Expand); in PPCTargetLowering()
129 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass); in PPCTargetLowering()
134 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom); in PPCTargetLowering()
137 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand); in PPCTargetLowering()
138 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand); in PPCTargetLowering()
139 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand); in PPCTargetLowering()
140 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand); in PPCTargetLowering()
141 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand); in PPCTargetLowering()
142 setOperationAction(ISD::FREM, MVT::ppcf128, Expand); in PPCTargetLowering()
145 setOperationAction(ISD::SREM, MVT::i32, Expand); in PPCTargetLowering()
146 setOperationAction(ISD::UREM, MVT::i32, Expand); in PPCTargetLowering()
147 setOperationAction(ISD::SREM, MVT::i64, Expand); in PPCTargetLowering()
148 setOperationAction(ISD::UREM, MVT::i64, Expand); in PPCTargetLowering()
151 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); in PPCTargetLowering()
152 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); in PPCTargetLowering()
153 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); in PPCTargetLowering()
154 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); in PPCTargetLowering()
155 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); in PPCTargetLowering()
156 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); in PPCTargetLowering()
157 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); in PPCTargetLowering()
158 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); in PPCTargetLowering()
161 setOperationAction(ISD::FSIN , MVT::f64, Expand); in PPCTargetLowering()
162 setOperationAction(ISD::FCOS , MVT::f64, Expand); in PPCTargetLowering()
163 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); in PPCTargetLowering()
164 setOperationAction(ISD::FREM , MVT::f64, Expand); in PPCTargetLowering()
165 setOperationAction(ISD::FPOW , MVT::f64, Expand); in PPCTargetLowering()
166 setOperationAction(ISD::FMA , MVT::f64, Legal); in PPCTargetLowering()
167 setOperationAction(ISD::FSIN , MVT::f32, Expand); in PPCTargetLowering()
168 setOperationAction(ISD::FCOS , MVT::f32, Expand); in PPCTargetLowering()
169 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); in PPCTargetLowering()
170 setOperationAction(ISD::FREM , MVT::f32, Expand); in PPCTargetLowering()
171 setOperationAction(ISD::FPOW , MVT::f32, Expand); in PPCTargetLowering()
172 setOperationAction(ISD::FMA , MVT::f32, Legal); in PPCTargetLowering()
174 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom); in PPCTargetLowering()
180 setOperationAction(ISD::FSQRT, MVT::f64, Expand); in PPCTargetLowering()
185 setOperationAction(ISD::FSQRT, MVT::f32, Expand); in PPCTargetLowering()
188 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal); in PPCTargetLowering()
189 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal); in PPCTargetLowering()
191 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); in PPCTargetLowering()
192 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); in PPCTargetLowering()
196 setOperationAction(ISD::FFLOOR, MVT::f64, Legal); in PPCTargetLowering()
197 setOperationAction(ISD::FCEIL, MVT::f64, Legal); in PPCTargetLowering()
198 setOperationAction(ISD::FTRUNC, MVT::f64, Legal); in PPCTargetLowering()
199 setOperationAction(ISD::FROUND, MVT::f64, Legal); in PPCTargetLowering()
201 setOperationAction(ISD::FFLOOR, MVT::f32, Legal); in PPCTargetLowering()
202 setOperationAction(ISD::FCEIL, MVT::f32, Legal); in PPCTargetLowering()
203 setOperationAction(ISD::FTRUNC, MVT::f32, Legal); in PPCTargetLowering()
204 setOperationAction(ISD::FROUND, MVT::f32, Legal); in PPCTargetLowering()
208 setOperationAction(ISD::BSWAP, MVT::i32 , Expand); in PPCTargetLowering()
209 setOperationAction(ISD::CTTZ , MVT::i32 , Expand); in PPCTargetLowering()
210 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand); in PPCTargetLowering()
211 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand); in PPCTargetLowering()
212 setOperationAction(ISD::BSWAP, MVT::i64 , Expand); in PPCTargetLowering()
213 setOperationAction(ISD::CTTZ , MVT::i64 , Expand); in PPCTargetLowering()
214 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand); in PPCTargetLowering()
215 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand); in PPCTargetLowering()
218 setOperationAction(ISD::CTPOP, MVT::i32 , Legal); in PPCTargetLowering()
219 setOperationAction(ISD::CTPOP, MVT::i64 , Legal); in PPCTargetLowering()
221 setOperationAction(ISD::CTPOP, MVT::i32 , Expand); in PPCTargetLowering()
222 setOperationAction(ISD::CTPOP, MVT::i64 , Expand); in PPCTargetLowering()
226 setOperationAction(ISD::ROTR, MVT::i32 , Expand); in PPCTargetLowering()
227 setOperationAction(ISD::ROTR, MVT::i64 , Expand); in PPCTargetLowering()
231 setOperationAction(ISD::SELECT, MVT::i32, Expand); in PPCTargetLowering()
232 setOperationAction(ISD::SELECT, MVT::i64, Expand); in PPCTargetLowering()
233 setOperationAction(ISD::SELECT, MVT::f32, Expand); in PPCTargetLowering()
234 setOperationAction(ISD::SELECT, MVT::f64, Expand); in PPCTargetLowering()
238 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); in PPCTargetLowering()
239 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); in PPCTargetLowering()
243 setOperationAction(ISD::SETCC, MVT::i32, Custom); in PPCTargetLowering()
247 setOperationAction(ISD::BRCOND, MVT::Other, Expand); in PPCTargetLowering()
249 setOperationAction(ISD::BR_JT, MVT::Other, Expand); in PPCTargetLowering()
252 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in PPCTargetLowering()
255 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); in PPCTargetLowering()
256 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); in PPCTargetLowering()
259 setOperationAction(ISD::BITCAST, MVT::f32, Legal); in PPCTargetLowering()
260 setOperationAction(ISD::BITCAST, MVT::i32, Legal); in PPCTargetLowering()
261 setOperationAction(ISD::BITCAST, MVT::i64, Legal); in PPCTargetLowering()
262 setOperationAction(ISD::BITCAST, MVT::f64, Legal); in PPCTargetLowering()
264 setOperationAction(ISD::BITCAST, MVT::f32, Expand); in PPCTargetLowering()
265 setOperationAction(ISD::BITCAST, MVT::i32, Expand); in PPCTargetLowering()
266 setOperationAction(ISD::BITCAST, MVT::i64, Expand); in PPCTargetLowering()
267 setOperationAction(ISD::BITCAST, MVT::f64, Expand); in PPCTargetLowering()
271 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in PPCTargetLowering()
279 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom); in PPCTargetLowering()
280 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom); in PPCTargetLowering()
284 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); in PPCTargetLowering()
285 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); in PPCTargetLowering()
286 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); in PPCTargetLowering()
287 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); in PPCTargetLowering()
288 setOperationAction(ISD::JumpTable, MVT::i32, Custom); in PPCTargetLowering()
289 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); in PPCTargetLowering()
290 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); in PPCTargetLowering()
291 setOperationAction(ISD::BlockAddress, MVT::i64, Custom); in PPCTargetLowering()
292 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); in PPCTargetLowering()
293 setOperationAction(ISD::JumpTable, MVT::i64, Custom); in PPCTargetLowering()
296 setOperationAction(ISD::TRAP, MVT::Other, Legal); in PPCTargetLowering()
299 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom); in PPCTargetLowering()
300 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom); in PPCTargetLowering()
303 setOperationAction(ISD::VASTART , MVT::Other, Custom); in PPCTargetLowering()
308 setOperationAction(ISD::VAARG, MVT::i1, Promote); in PPCTargetLowering()
309 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64); in PPCTargetLowering()
310 setOperationAction(ISD::VAARG, MVT::i8, Promote); in PPCTargetLowering()
311 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64); in PPCTargetLowering()
312 setOperationAction(ISD::VAARG, MVT::i16, Promote); in PPCTargetLowering()
313 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64); in PPCTargetLowering()
314 setOperationAction(ISD::VAARG, MVT::i32, Promote); in PPCTargetLowering()
315 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64); in PPCTargetLowering()
316 setOperationAction(ISD::VAARG, MVT::Other, Expand); in PPCTargetLowering()
319 setOperationAction(ISD::VAARG, MVT::Other, Custom); in PPCTargetLowering()
320 setOperationAction(ISD::VAARG, MVT::i64, Custom); in PPCTargetLowering()
323 setOperationAction(ISD::VAARG, MVT::Other, Expand); in PPCTargetLowering()
327 setOperationAction(ISD::VACOPY , MVT::Other, Custom); in PPCTargetLowering()
329 setOperationAction(ISD::VACOPY , MVT::Other, Expand); in PPCTargetLowering()
332 setOperationAction(ISD::VAEND , MVT::Other, Expand); in PPCTargetLowering()
333 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); in PPCTargetLowering()
334 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom); in PPCTargetLowering()
335 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); in PPCTargetLowering()
336 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom); in PPCTargetLowering()
337 setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, MVT::i32, Custom); in PPCTargetLowering()
338 setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, MVT::i64, Custom); in PPCTargetLowering()
341 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); in PPCTargetLowering()
344 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom); in PPCTargetLowering()
347 setCondCodeAction(ISD::SETULT, MVT::f32, Expand); in PPCTargetLowering()
348 setCondCodeAction(ISD::SETULT, MVT::f64, Expand); in PPCTargetLowering()
349 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand); in PPCTargetLowering()
350 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand); in PPCTargetLowering()
351 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand); in PPCTargetLowering()
352 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand); in PPCTargetLowering()
353 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand); in PPCTargetLowering()
354 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand); in PPCTargetLowering()
355 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand); in PPCTargetLowering()
356 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand); in PPCTargetLowering()
357 setCondCodeAction(ISD::SETONE, MVT::f32, Expand); in PPCTargetLowering()
358 setCondCodeAction(ISD::SETONE, MVT::f64, Expand); in PPCTargetLowering()
362 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in PPCTargetLowering()
363 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); in PPCTargetLowering()
364 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); in PPCTargetLowering()
365 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); in PPCTargetLowering()
368 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); in PPCTargetLowering()
371 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); in PPCTargetLowering()
374 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); in PPCTargetLowering()
380 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in PPCTargetLowering()
381 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom); in PPCTargetLowering()
382 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); in PPCTargetLowering()
383 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom); in PPCTargetLowering()
386 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in PPCTargetLowering()
387 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); in PPCTargetLowering()
388 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); in PPCTargetLowering()
389 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); in PPCTargetLowering()
394 addRegisterClass(MVT::i64, &PPC::G8RCRegClass); in PPCTargetLowering()
396 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand); in PPCTargetLowering()
398 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom); in PPCTargetLowering()
399 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom); in PPCTargetLowering()
400 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom); in PPCTargetLowering()
403 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); in PPCTargetLowering()
404 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); in PPCTargetLowering()
405 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); in PPCTargetLowering()
411 for (MVT VT : MVT::vector_valuetypes()) { in PPCTargetLowering()
417 if (Subtarget.hasP8Altivec() && (VT.SimpleTy != MVT::v1i128)) { in PPCTargetLowering()
428 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8); in PPCTargetLowering()
432 AddPromotedToType (ISD::AND , VT, MVT::v4i32); in PPCTargetLowering()
434 AddPromotedToType (ISD::OR , VT, MVT::v4i32); in PPCTargetLowering()
436 AddPromotedToType (ISD::XOR , VT, MVT::v4i32); in PPCTargetLowering()
438 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32); in PPCTargetLowering()
440 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32); in PPCTargetLowering()
442 AddPromotedToType (ISD::SELECT_CC, VT, MVT::v4i32); in PPCTargetLowering()
444 AddPromotedToType (ISD::STORE, VT, MVT::v4i32); in PPCTargetLowering()
490 for (MVT InnerVT : MVT::vector_valuetypes()) { in PPCTargetLowering()
500 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom); in PPCTargetLowering()
502 setOperationAction(ISD::AND , MVT::v4i32, Legal); in PPCTargetLowering()
503 setOperationAction(ISD::OR , MVT::v4i32, Legal); in PPCTargetLowering()
504 setOperationAction(ISD::XOR , MVT::v4i32, Legal); in PPCTargetLowering()
505 setOperationAction(ISD::LOAD , MVT::v4i32, Legal); in PPCTargetLowering()
506 setOperationAction(ISD::SELECT, MVT::v4i32, in PPCTargetLowering()
508 setOperationAction(ISD::STORE , MVT::v4i32, Legal); in PPCTargetLowering()
509 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal); in PPCTargetLowering()
510 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal); in PPCTargetLowering()
511 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal); in PPCTargetLowering()
512 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal); in PPCTargetLowering()
513 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal); in PPCTargetLowering()
514 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal); in PPCTargetLowering()
515 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal); in PPCTargetLowering()
516 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal); in PPCTargetLowering()
518 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass); in PPCTargetLowering()
519 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass); in PPCTargetLowering()
520 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass); in PPCTargetLowering()
521 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass); in PPCTargetLowering()
523 setOperationAction(ISD::MUL, MVT::v4f32, Legal); in PPCTargetLowering()
524 setOperationAction(ISD::FMA, MVT::v4f32, Legal); in PPCTargetLowering()
527 setOperationAction(ISD::FDIV, MVT::v4f32, Legal); in PPCTargetLowering()
528 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); in PPCTargetLowering()
532 setOperationAction(ISD::MUL, MVT::v4i32, Legal); in PPCTargetLowering()
534 setOperationAction(ISD::MUL, MVT::v4i32, Custom); in PPCTargetLowering()
536 setOperationAction(ISD::MUL, MVT::v8i16, Custom); in PPCTargetLowering()
537 setOperationAction(ISD::MUL, MVT::v16i8, Custom); in PPCTargetLowering()
539 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom); in PPCTargetLowering()
540 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom); in PPCTargetLowering()
542 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom); in PPCTargetLowering()
543 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom); in PPCTargetLowering()
544 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom); in PPCTargetLowering()
545 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); in PPCTargetLowering()
548 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand); in PPCTargetLowering()
549 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand); in PPCTargetLowering()
550 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand); in PPCTargetLowering()
551 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand); in PPCTargetLowering()
554 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal); in PPCTargetLowering()
555 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal); in PPCTargetLowering()
557 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal); in PPCTargetLowering()
558 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Legal); in PPCTargetLowering()
561 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Legal); in PPCTargetLowering()
562 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Legal); in PPCTargetLowering()
563 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Legal); in PPCTargetLowering()
564 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i64, Legal); in PPCTargetLowering()
565 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Legal); in PPCTargetLowering()
566 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Legal); in PPCTargetLowering()
567 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Legal); in PPCTargetLowering()
568 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal); in PPCTargetLowering()
570 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal); in PPCTargetLowering()
572 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal); in PPCTargetLowering()
573 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal); in PPCTargetLowering()
574 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal); in PPCTargetLowering()
575 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal); in PPCTargetLowering()
576 setOperationAction(ISD::FROUND, MVT::v2f64, Legal); in PPCTargetLowering()
578 setOperationAction(ISD::FROUND, MVT::v4f32, Legal); in PPCTargetLowering()
580 setOperationAction(ISD::MUL, MVT::v2f64, Legal); in PPCTargetLowering()
581 setOperationAction(ISD::FMA, MVT::v2f64, Legal); in PPCTargetLowering()
583 setOperationAction(ISD::FDIV, MVT::v2f64, Legal); in PPCTargetLowering()
584 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal); in PPCTargetLowering()
586 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal); in PPCTargetLowering()
587 setOperationAction(ISD::VSELECT, MVT::v8i16, Legal); in PPCTargetLowering()
588 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal); in PPCTargetLowering()
589 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal); in PPCTargetLowering()
590 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal); in PPCTargetLowering()
593 setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand); in PPCTargetLowering()
594 setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand); in PPCTargetLowering()
595 setCondCodeAction(ISD::SETO, MVT::v2f64, Expand); in PPCTargetLowering()
596 setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand); in PPCTargetLowering()
598 setOperationAction(ISD::LOAD, MVT::v2f64, Legal); in PPCTargetLowering()
599 setOperationAction(ISD::STORE, MVT::v2f64, Legal); in PPCTargetLowering()
601 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Legal); in PPCTargetLowering()
604 addRegisterClass(MVT::f32, &PPC::VSSRCRegClass); in PPCTargetLowering()
606 addRegisterClass(MVT::f64, &PPC::VSFRCRegClass); in PPCTargetLowering()
608 addRegisterClass(MVT::v4i32, &PPC::VSRCRegClass); in PPCTargetLowering()
609 addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass); in PPCTargetLowering()
610 addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass); in PPCTargetLowering()
613 setOperationAction(ISD::SHL, MVT::v2i64, Legal); in PPCTargetLowering()
614 setOperationAction(ISD::SRA, MVT::v2i64, Legal); in PPCTargetLowering()
615 setOperationAction(ISD::SRL, MVT::v2i64, Legal); in PPCTargetLowering()
617 setOperationAction(ISD::SETCC, MVT::v2i64, Legal); in PPCTargetLowering()
620 setOperationAction(ISD::SHL, MVT::v2i64, Expand); in PPCTargetLowering()
621 setOperationAction(ISD::SRA, MVT::v2i64, Expand); in PPCTargetLowering()
622 setOperationAction(ISD::SRL, MVT::v2i64, Expand); in PPCTargetLowering()
624 setOperationAction(ISD::SETCC, MVT::v2i64, Custom); in PPCTargetLowering()
627 setOperationAction(ISD::ADD, MVT::v2i64, Expand); in PPCTargetLowering()
628 setOperationAction(ISD::SUB, MVT::v2i64, Expand); in PPCTargetLowering()
631 setOperationAction(ISD::LOAD, MVT::v2i64, Promote); in PPCTargetLowering()
632 AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64); in PPCTargetLowering()
633 setOperationAction(ISD::STORE, MVT::v2i64, Promote); in PPCTargetLowering()
634 AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64); in PPCTargetLowering()
636 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal); in PPCTargetLowering()
638 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal); in PPCTargetLowering()
639 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal); in PPCTargetLowering()
640 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal); in PPCTargetLowering()
641 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal); in PPCTargetLowering()
645 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal); in PPCTargetLowering()
646 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal); in PPCTargetLowering()
647 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom); in PPCTargetLowering()
648 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom); in PPCTargetLowering()
650 addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass); in PPCTargetLowering()
654 addRegisterClass(MVT::v2i64, &PPC::VRRCRegClass); in PPCTargetLowering()
655 addRegisterClass(MVT::v1i128, &PPC::VRRCRegClass); in PPCTargetLowering()
660 setOperationAction(ISD::FADD, MVT::v4f64, Legal); in PPCTargetLowering()
661 setOperationAction(ISD::FSUB, MVT::v4f64, Legal); in PPCTargetLowering()
662 setOperationAction(ISD::FMUL, MVT::v4f64, Legal); in PPCTargetLowering()
663 setOperationAction(ISD::FREM, MVT::v4f64, Expand); in PPCTargetLowering()
665 setOperationAction(ISD::FCOPYSIGN, MVT::v4f64, Legal); in PPCTargetLowering()
666 setOperationAction(ISD::FGETSIGN, MVT::v4f64, Expand); in PPCTargetLowering()
668 setOperationAction(ISD::LOAD , MVT::v4f64, Custom); in PPCTargetLowering()
669 setOperationAction(ISD::STORE , MVT::v4f64, Custom); in PPCTargetLowering()
671 setTruncStoreAction(MVT::v4f64, MVT::v4f32, Custom); in PPCTargetLowering()
672 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f32, Custom); in PPCTargetLowering()
675 setOperationAction(ISD::SELECT, MVT::v4f64, Expand); in PPCTargetLowering()
676 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal); in PPCTargetLowering()
678 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4f64, Legal); in PPCTargetLowering()
679 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4f64, Expand); in PPCTargetLowering()
680 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4f64, Expand); in PPCTargetLowering()
681 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4f64, Expand); in PPCTargetLowering()
682 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4f64, Custom); in PPCTargetLowering()
683 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f64, Legal); in PPCTargetLowering()
684 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom); in PPCTargetLowering()
686 setOperationAction(ISD::FP_TO_SINT , MVT::v4f64, Legal); in PPCTargetLowering()
687 setOperationAction(ISD::FP_TO_UINT , MVT::v4f64, Expand); in PPCTargetLowering()
689 setOperationAction(ISD::FP_ROUND , MVT::v4f32, Legal); in PPCTargetLowering()
690 setOperationAction(ISD::FP_ROUND_INREG , MVT::v4f32, Expand); in PPCTargetLowering()
691 setOperationAction(ISD::FP_EXTEND, MVT::v4f64, Legal); in PPCTargetLowering()
693 setOperationAction(ISD::FNEG , MVT::v4f64, Legal); in PPCTargetLowering()
694 setOperationAction(ISD::FABS , MVT::v4f64, Legal); in PPCTargetLowering()
695 setOperationAction(ISD::FSIN , MVT::v4f64, Expand); in PPCTargetLowering()
696 setOperationAction(ISD::FCOS , MVT::v4f64, Expand); in PPCTargetLowering()
697 setOperationAction(ISD::FPOWI , MVT::v4f64, Expand); in PPCTargetLowering()
698 setOperationAction(ISD::FPOW , MVT::v4f64, Expand); in PPCTargetLowering()
699 setOperationAction(ISD::FLOG , MVT::v4f64, Expand); in PPCTargetLowering()
700 setOperationAction(ISD::FLOG2 , MVT::v4f64, Expand); in PPCTargetLowering()
701 setOperationAction(ISD::FLOG10 , MVT::v4f64, Expand); in PPCTargetLowering()
702 setOperationAction(ISD::FEXP , MVT::v4f64, Expand); in PPCTargetLowering()
703 setOperationAction(ISD::FEXP2 , MVT::v4f64, Expand); in PPCTargetLowering()
705 setOperationAction(ISD::FMINNUM, MVT::v4f64, Legal); in PPCTargetLowering()
706 setOperationAction(ISD::FMAXNUM, MVT::v4f64, Legal); in PPCTargetLowering()
708 setIndexedLoadAction(ISD::PRE_INC, MVT::v4f64, Legal); in PPCTargetLowering()
709 setIndexedStoreAction(ISD::PRE_INC, MVT::v4f64, Legal); in PPCTargetLowering()
711 addRegisterClass(MVT::v4f64, &PPC::QFRCRegClass); in PPCTargetLowering()
713 setOperationAction(ISD::FADD, MVT::v4f32, Legal); in PPCTargetLowering()
714 setOperationAction(ISD::FSUB, MVT::v4f32, Legal); in PPCTargetLowering()
715 setOperationAction(ISD::FMUL, MVT::v4f32, Legal); in PPCTargetLowering()
716 setOperationAction(ISD::FREM, MVT::v4f32, Expand); in PPCTargetLowering()
718 setOperationAction(ISD::FCOPYSIGN, MVT::v4f32, Legal); in PPCTargetLowering()
719 setOperationAction(ISD::FGETSIGN, MVT::v4f32, Expand); in PPCTargetLowering()
721 setOperationAction(ISD::LOAD , MVT::v4f32, Custom); in PPCTargetLowering()
722 setOperationAction(ISD::STORE , MVT::v4f32, Custom); in PPCTargetLowering()
725 setOperationAction(ISD::SELECT, MVT::v4f32, Expand); in PPCTargetLowering()
726 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal); in PPCTargetLowering()
728 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4f32, Legal); in PPCTargetLowering()
729 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4f32, Expand); in PPCTargetLowering()
730 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4f32, Expand); in PPCTargetLowering()
731 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4f32, Expand); in PPCTargetLowering()
732 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4f32, Custom); in PPCTargetLowering()
733 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal); in PPCTargetLowering()
734 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); in PPCTargetLowering()
736 setOperationAction(ISD::FP_TO_SINT , MVT::v4f32, Legal); in PPCTargetLowering()
737 setOperationAction(ISD::FP_TO_UINT , MVT::v4f32, Expand); in PPCTargetLowering()
739 setOperationAction(ISD::FNEG , MVT::v4f32, Legal); in PPCTargetLowering()
740 setOperationAction(ISD::FABS , MVT::v4f32, Legal); in PPCTargetLowering()
741 setOperationAction(ISD::FSIN , MVT::v4f32, Expand); in PPCTargetLowering()
742 setOperationAction(ISD::FCOS , MVT::v4f32, Expand); in PPCTargetLowering()
743 setOperationAction(ISD::FPOWI , MVT::v4f32, Expand); in PPCTargetLowering()
744 setOperationAction(ISD::FPOW , MVT::v4f32, Expand); in PPCTargetLowering()
745 setOperationAction(ISD::FLOG , MVT::v4f32, Expand); in PPCTargetLowering()
746 setOperationAction(ISD::FLOG2 , MVT::v4f32, Expand); in PPCTargetLowering()
747 setOperationAction(ISD::FLOG10 , MVT::v4f32, Expand); in PPCTargetLowering()
748 setOperationAction(ISD::FEXP , MVT::v4f32, Expand); in PPCTargetLowering()
749 setOperationAction(ISD::FEXP2 , MVT::v4f32, Expand); in PPCTargetLowering()
751 setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal); in PPCTargetLowering()
752 setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal); in PPCTargetLowering()
754 setIndexedLoadAction(ISD::PRE_INC, MVT::v4f32, Legal); in PPCTargetLowering()
755 setIndexedStoreAction(ISD::PRE_INC, MVT::v4f32, Legal); in PPCTargetLowering()
757 addRegisterClass(MVT::v4f32, &PPC::QSRCRegClass); in PPCTargetLowering()
759 setOperationAction(ISD::AND , MVT::v4i1, Legal); in PPCTargetLowering()
760 setOperationAction(ISD::OR , MVT::v4i1, Legal); in PPCTargetLowering()
761 setOperationAction(ISD::XOR , MVT::v4i1, Legal); in PPCTargetLowering()
764 setOperationAction(ISD::SELECT, MVT::v4i1, Expand); in PPCTargetLowering()
765 setOperationAction(ISD::VSELECT, MVT::v4i1, Legal); in PPCTargetLowering()
767 setOperationAction(ISD::LOAD , MVT::v4i1, Custom); in PPCTargetLowering()
768 setOperationAction(ISD::STORE , MVT::v4i1, Custom); in PPCTargetLowering()
770 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4i1, Custom); in PPCTargetLowering()
771 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4i1, Expand); in PPCTargetLowering()
772 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4i1, Expand); in PPCTargetLowering()
773 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4i1, Expand); in PPCTargetLowering()
774 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4i1, Custom); in PPCTargetLowering()
775 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i1, Expand); in PPCTargetLowering()
776 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i1, Custom); in PPCTargetLowering()
778 setOperationAction(ISD::SINT_TO_FP, MVT::v4i1, Custom); in PPCTargetLowering()
779 setOperationAction(ISD::UINT_TO_FP, MVT::v4i1, Custom); in PPCTargetLowering()
781 addRegisterClass(MVT::v4i1, &PPC::QBRCRegClass); in PPCTargetLowering()
783 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal); in PPCTargetLowering()
784 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal); in PPCTargetLowering()
785 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal); in PPCTargetLowering()
786 setOperationAction(ISD::FROUND, MVT::v4f64, Legal); in PPCTargetLowering()
788 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal); in PPCTargetLowering()
789 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal); in PPCTargetLowering()
790 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal); in PPCTargetLowering()
791 setOperationAction(ISD::FROUND, MVT::v4f32, Legal); in PPCTargetLowering()
793 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Expand); in PPCTargetLowering()
794 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand); in PPCTargetLowering()
797 setOperationAction(ISD::FRINT, MVT::v4f64, Expand); in PPCTargetLowering()
798 setOperationAction(ISD::FRINT, MVT::v4f32, Expand); in PPCTargetLowering()
801 setOperationAction(ISD::FDIV, MVT::v4f64, Legal); in PPCTargetLowering()
802 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal); in PPCTargetLowering()
804 setOperationAction(ISD::FDIV, MVT::v4f32, Legal); in PPCTargetLowering()
805 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); in PPCTargetLowering()
807 setOperationAction(ISD::FDIV, MVT::v4f64, Expand); in PPCTargetLowering()
808 setOperationAction(ISD::FSQRT, MVT::v4f64, Expand); in PPCTargetLowering()
810 setOperationAction(ISD::FDIV, MVT::v4f32, Expand); in PPCTargetLowering()
811 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand); in PPCTargetLowering()
816 setOperationAction(ISD::PREFETCH, MVT::Other, Legal); in PPCTargetLowering()
818 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, isPPC64 ? Legal : Custom); in PPCTargetLowering()
821 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand); in PPCTargetLowering()
822 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand); in PPCTargetLowering()
1085 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32; in getSetCCResultType()
1088 return EVT::getVectorVT(C, MVT::i1, VT.getVectorNumElements()); in getSetCCResultType()
1241 if (N->getValueType(0) != MVT::v16i8) in isVMerge()
1351 if (N->getValueType(0) != MVT::v16i8) in isVMerge()
1409 if (N->getValueType(0) != MVT::v16i8) in isVSLDOIShuffleMask()
1452 assert(N->getValueType(0) == MVT::v16i8 && in isSplatShuffleMask()
1542 return DAG.getTargetConstant(0, SDLoc(N), MVT::i32); // 0,0,0,undef in get_VSPLTI_elt()
1545 return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32); in get_VSPLTI_elt()
1549 return DAG.getTargetConstant(~0U, SDLoc(N), MVT::i32); // -1,-1,-1,undef in get_VSPLTI_elt()
1552 return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32); in get_VSPLTI_elt()
1574 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!"); in get_VSPLTI_elt()
1596 return DAG.getTargetConstant(MaskVal, SDLoc(N), MVT::i32); in get_VSPLTI_elt()
1604 if (VT != MVT::v4f64 && VT != MVT::v4f32 && VT != MVT::v4i1) in isQVALIGNIShuffleMask()
1643 if (N->getValueType(0) == MVT::i32) in isIntS16Immediate()
1706 if (VT != MVT::i64) in fixupFuncForFI()
1812 if ((CN->getValueType(0) == MVT::i32 || in SelectAddressRegImm()
1818 Disp = DAG.getTargetConstant((short)Addr, dl, MVT::i32); in SelectAddressRegImm()
1821 MVT::i32); in SelectAddressRegImm()
1822 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; in SelectAddressRegImm()
1892 if (!Subtarget.hasQPX() || (VT != MVT::v4f64 && VT != MVT::v4f32)) { in getPreIndexedAddressParts()
1924 if (VT != MVT::i64) { in getPreIndexedAddressParts()
1939 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 && in getPreIndexedAddressParts()
2015 EVT VT = Is64Bit ? MVT::i64 : MVT::i32; in getTOCEntry()
2021 PPCISD::TOC_ENTRY, dl, DAG.getVTList(VT, MVT::Other), Ops, VT, in getTOCEntry()
2132 is64bit ? MVT::i64 : MVT::i32); in LowerGlobalTLSAddress()
2144 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64); in LowerGlobalTLSAddress()
2159 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64); in LowerGlobalTLSAddress()
2177 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64); in LowerGlobalTLSAddress()
2241 if (Op.getValueType() == MVT::v2i64) { in LowerSETCC()
2244 if (Op.getOperand(0).getValueType() == MVT::v2i64) { in LowerSETCC()
2248 return DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, in LowerSETCC()
2249 DAG.getSetCC(dl, MVT::v4i32, in LowerSETCC()
2250 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0)), in LowerSETCC()
2251 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(1)), in LowerSETCC()
2269 if (VT.bitsLT(MVT::i32)) { in LowerSETCC()
2270 VT = MVT::i32; in LowerSETCC()
2276 DAG.getConstant(Log2b, dl, MVT::i32)); in LowerSETCC()
2277 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc); in LowerSETCC()
2314 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain, in LowerVAARG()
2315 VAListPtr, MachinePointerInfo(SV), MVT::i8, in LowerVAARG()
2319 if (VT == MVT::i64) { in LowerVAARG()
2321 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex, in LowerVAARG()
2322 DAG.getConstant(1, dl, MVT::i32)); in LowerVAARG()
2323 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd, in LowerVAARG()
2324 DAG.getConstant(0, dl, MVT::i32), ISD::SETNE); in LowerVAARG()
2325 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex, in LowerVAARG()
2326 DAG.getConstant(1, dl, MVT::i32)); in LowerVAARG()
2328 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne, in LowerVAARG()
2334 DAG.getConstant(1, dl, MVT::i32)); in LowerVAARG()
2337 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain, in LowerVAARG()
2338 FprPtr, MachinePointerInfo(SV), MVT::i8, in LowerVAARG()
2343 DAG.getConstant(8, dl, MVT::i32)); in LowerVAARG()
2346 DAG.getConstant(4, dl, MVT::i32)); in LowerVAARG()
2349 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr, in LowerVAARG()
2354 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr, in LowerVAARG()
2360 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex, in LowerVAARG()
2361 DAG.getConstant(8, dl, MVT::i32), ISD::SETLT); in LowerVAARG()
2364 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32, in LowerVAARG()
2367 MVT::i32)); in LowerVAARG()
2376 DAG.getConstant(32, dl, MVT::i32)); in LowerVAARG()
2379 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32, in LowerVAARG()
2381 DAG.getConstant(VT == MVT::i64 ? 2 : 1, dl, in LowerVAARG()
2382 MVT::i32)); in LowerVAARG()
2387 MVT::i8, false, false, 0); in LowerVAARG()
2395 dl, MVT::i32)); in LowerVAARG()
2397 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea, in LowerVAARG()
2403 MVT::i32, false, false, 0); in LowerVAARG()
2417 DAG.getConstant(12, SDLoc(Op), MVT::i32), 8, false, true, in LowerVACOPY()
2435 bool isPPC64 = (PtrVT == MVT::i64); in LowerINIT_TRAMPOLINE()
2446 isPPC64 ? MVT::i64 : MVT::i32); in LowerINIT_TRAMPOLINE()
2505 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), dl, MVT::i32); in LowerVASTART()
2506 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), dl, MVT::i32); in LowerVASTART()
2530 MVT::i8, false, false, 0); in LowerVASTART()
2538 MachinePointerInfo(SV, nextOffset), MVT::i8, in LowerVASTART()
2566 bool llvm::CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT, in CC_PPC32_SVR4_Custom_Dummy()
2573 bool llvm::CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT, in CC_PPC32_SVR4_Custom_AlignArgRegs()
2574 MVT &LocVT, in CC_PPC32_SVR4_Custom_AlignArgRegs()
2600 bool llvm::CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT, in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
2601 MVT &LocVT, in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
2662 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 || in CalculateStackSlotAlignment()
2663 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 || in CalculateStackSlotAlignment()
2664 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64 || in CalculateStackSlotAlignment()
2665 ArgVT == MVT::v1i128) in CalculateStackSlotAlignment()
2669 else if (ArgVT == MVT::v4f64 || ArgVT == MVT::v4i1) in CalculateStackSlotAlignment()
2689 if (Flags.isSplit() && OrigVT != MVT::ppcf128) in CalculateStackSlotAlignment()
2733 if (ArgVT == MVT::f32 || ArgVT == MVT::f64 || in CalculateStackSlotUsed()
2735 (HasQPX && (ArgVT == MVT::v4f32 || in CalculateStackSlotUsed()
2736 ArgVT == MVT::v4f64 || in CalculateStackSlotUsed()
2737 ArgVT == MVT::v4i1))) in CalculateStackSlotUsed()
2742 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 || in CalculateStackSlotUsed()
2743 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 || in CalculateStackSlotUsed()
2744 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64 || in CalculateStackSlotUsed()
2745 ArgVT == MVT::v1i128) in CalculateStackSlotUsed()
2856 case MVT::i1: in LowerFormalArguments_32SVR4()
2857 case MVT::i32: in LowerFormalArguments_32SVR4()
2860 case MVT::f32: in LowerFormalArguments_32SVR4()
2866 case MVT::f64: in LowerFormalArguments_32SVR4()
2872 case MVT::v16i8: in LowerFormalArguments_32SVR4()
2873 case MVT::v8i16: in LowerFormalArguments_32SVR4()
2874 case MVT::v4i32: in LowerFormalArguments_32SVR4()
2877 case MVT::v4f32: in LowerFormalArguments_32SVR4()
2880 case MVT::v2f64: in LowerFormalArguments_32SVR4()
2881 case MVT::v2i64: in LowerFormalArguments_32SVR4()
2884 case MVT::v4f64: in LowerFormalArguments_32SVR4()
2887 case MVT::v4i1: in LowerFormalArguments_32SVR4()
2895 ValVT == MVT::i1 ? MVT::i32 : ValVT); in LowerFormalArguments_32SVR4()
2897 if (ValVT == MVT::i1) in LowerFormalArguments_32SVR4()
2898 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue); in LowerFormalArguments_32SVR4()
2966 NumFPArgRegs * MVT(MVT::f64).getSizeInBits()/8; in LowerFormalArguments_32SVR4()
3003 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64); in LowerFormalArguments_32SVR4()
3008 SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8, dl, in LowerFormalArguments_32SVR4()
3015 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps); in LowerFormalArguments_32SVR4()
3027 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal, in extendArgForPPC64()
3030 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal, in extendArgForPPC64()
3199 EVT ObjType = (ObjSize == 1 ? MVT::i8 : in LowerFormalArguments_64SVR4()
3200 (ObjSize == 2 ? MVT::i16 : MVT::i32)); in LowerFormalArguments_64SVR4()
3249 case MVT::i1: in LowerFormalArguments_64SVR4()
3250 case MVT::i32: in LowerFormalArguments_64SVR4()
3251 case MVT::i64: in LowerFormalArguments_64SVR4()
3255 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); in LowerFormalArguments_64SVR4()
3257 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1) in LowerFormalArguments_64SVR4()
3268 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); in LowerFormalArguments_64SVR4()
3270 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1) in LowerFormalArguments_64SVR4()
3285 case MVT::f32: in LowerFormalArguments_64SVR4()
3286 case MVT::f64: in LowerFormalArguments_64SVR4()
3293 if (ObjectVT == MVT::f32) in LowerFormalArguments_64SVR4()
3313 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); in LowerFormalArguments_64SVR4()
3315 if (ObjectVT == MVT::f32) { in LowerFormalArguments_64SVR4()
3317 ArgVal = DAG.getNode(ISD::SRL, dl, MVT::i64, ArgVal, in LowerFormalArguments_64SVR4()
3318 DAG.getConstant(32, dl, MVT::i32)); in LowerFormalArguments_64SVR4()
3319 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal); in LowerFormalArguments_64SVR4()
3340 case MVT::v4f32: in LowerFormalArguments_64SVR4()
3341 case MVT::v4i32: in LowerFormalArguments_64SVR4()
3342 case MVT::v8i16: in LowerFormalArguments_64SVR4()
3343 case MVT::v16i8: in LowerFormalArguments_64SVR4()
3344 case MVT::v2f64: in LowerFormalArguments_64SVR4()
3345 case MVT::v2i64: in LowerFormalArguments_64SVR4()
3346 case MVT::v1i128: in LowerFormalArguments_64SVR4()
3352 unsigned VReg = (ObjectVT == MVT::v2f64 || ObjectVT == MVT::v2i64) ? in LowerFormalArguments_64SVR4()
3368 assert(ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 && in LowerFormalArguments_64SVR4()
3372 case MVT::v4f64: in LowerFormalArguments_64SVR4()
3373 case MVT::v4i1: in LowerFormalArguments_64SVR4()
3376 unsigned Sz = ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 ? 16 : 32; in LowerFormalArguments_64SVR4()
3380 case MVT::v4f64: RC = &PPC::QFRCRegClass; break; in LowerFormalArguments_64SVR4()
3381 case MVT::v4f32: RC = &PPC::QSRCRegClass; break; in LowerFormalArguments_64SVR4()
3453 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps); in LowerFormalArguments_64SVR4()
3473 bool isPPC64 = PtrVT == MVT::i64; in LowerFormalArguments_Darwin()
3529 case MVT::i1: in LowerFormalArguments_Darwin()
3530 case MVT::i32: in LowerFormalArguments_Darwin()
3531 case MVT::f32: in LowerFormalArguments_Darwin()
3534 case MVT::i64: // PPC64 in LowerFormalArguments_Darwin()
3535 case MVT::f64: in LowerFormalArguments_Darwin()
3540 case MVT::v4f32: in LowerFormalArguments_Darwin()
3541 case MVT::v4i32: in LowerFormalArguments_Darwin()
3542 case MVT::v8i16: in LowerFormalArguments_Darwin()
3543 case MVT::v16i8: in LowerFormalArguments_Darwin()
3576 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 || in LowerFormalArguments_Darwin()
3577 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) { in LowerFormalArguments_Darwin()
3615 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16; in LowerFormalArguments_Darwin()
3656 case MVT::i1: in LowerFormalArguments_Darwin()
3657 case MVT::i32: in LowerFormalArguments_Darwin()
3661 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); in LowerFormalArguments_Darwin()
3663 if (ObjectVT == MVT::i1) in LowerFormalArguments_Darwin()
3664 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgVal); in LowerFormalArguments_Darwin()
3676 case MVT::i64: // PPC64 in LowerFormalArguments_Darwin()
3679 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); in LowerFormalArguments_Darwin()
3681 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1) in LowerFormalArguments_Darwin()
3695 case MVT::f32: in LowerFormalArguments_Darwin()
3696 case MVT::f64: in LowerFormalArguments_Darwin()
3707 if (ObjectVT == MVT::f32) in LowerFormalArguments_Darwin()
3721 case MVT::v4f32: in LowerFormalArguments_Darwin()
3722 case MVT::v4i32: in LowerFormalArguments_Darwin()
3723 case MVT::v8i16: in LowerFormalArguments_Darwin()
3724 case MVT::v16i8: in LowerFormalArguments_Darwin()
3819 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps); in LowerFormalArguments_Darwin()
3945 EVT VT = isPPC64 ? MVT::i64 : MVT::i32; in EmitTailCallStoreFPAndRetAddr()
3977 EVT VT = isPPC64 ? MVT::i64 : MVT::i32; in CalculateTailCallArgDest()
3998 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32; in EmitTailCallLoadFPAndRetAddr()
4026 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32); in CreateCopyOfByValArgument()
4046 StackPtr = DAG.getRegister(PPC::X1, MVT::i64); in LowerMemOpCallTo()
4048 StackPtr = DAG.getRegister(PPC::R1, MVT::i32); in LowerMemOpCallTo()
4074 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2); in PrepareTailCall()
4113 NodeTys.push_back(MVT::Other); // Returns a chain in PrepareCall()
4114 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use. in PrepareCall()
4217 if (LDChain.getValueType() == MVT::Glue) in PrepareCall()
4223 SDValue LoadFuncPtr = DAG.getLoad(MVT::i64, dl, LDChain, Callee, MPI, in PrepareCall()
4228 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff); in PrepareCall()
4229 SDValue LoadEnvPtr = DAG.getLoad(MVT::i64, dl, LDChain, AddPtr, in PrepareCall()
4234 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, TOCOff); in PrepareCall()
4235 SDValue TOCPtr = DAG.getLoad(MVT::i64, dl, LDChain, AddTOC, in PrepareCall()
4265 NodeTys.push_back(MVT::Other); in PrepareCall()
4266 NodeTys.push_back(MVT::Glue); in PrepareCall()
4285 Ops.push_back(DAG.getConstant(SPDiff, dl, MVT::i32)); in PrepareCall()
4378 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32)); in FinishCall()
4407 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, Ops); in FinishCall()
4437 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, StackPtr, TOCOff); in FinishCall()
4551 MVT ArgVT = Outs[i].VT; in LowerCall_32SVR4()
4610 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32); in LowerCall_32SVR4()
4663 if (Arg.getValueType() == MVT::i1) in LowerCall_32SVR4()
4664 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Arg); in LowerCall_32SVR4()
4691 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains); in LowerCall_32SVR4()
4705 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue); in LowerCall_32SVR4()
4823 case MVT::i1: in LowerCall_64SVR4()
4824 case MVT::i32: in LowerCall_64SVR4()
4825 case MVT::i64: in LowerCall_64SVR4()
4829 case MVT::v4i32: in LowerCall_64SVR4()
4830 case MVT::v8i16: in LowerCall_64SVR4()
4831 case MVT::v16i8: in LowerCall_64SVR4()
4832 case MVT::v2f64: in LowerCall_64SVR4()
4833 case MVT::v2i64: in LowerCall_64SVR4()
4834 case MVT::v1i128: in LowerCall_64SVR4()
4838 case MVT::v4f32: in LowerCall_64SVR4()
4849 case MVT::f32: in LowerCall_64SVR4()
4850 case MVT::f64: in LowerCall_64SVR4()
4851 case MVT::v4f64: // QPX in LowerCall_64SVR4()
4852 case MVT::v4i1: // QPX in LowerCall_64SVR4()
4908 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64); in LowerCall_64SVR4()
4953 if (Arg.getValueType() == MVT::i32 || Arg.getValueType() == MVT::i1) { in LowerCall_64SVR4()
4956 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg); in LowerCall_64SVR4()
4980 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32); in LowerCall_64SVR4()
5077 case MVT::i1: in LowerCall_64SVR4()
5078 case MVT::i32: in LowerCall_64SVR4()
5079 case MVT::i64: in LowerCall_64SVR4()
5105 case MVT::f32: in LowerCall_64SVR4()
5106 case MVT::f64: { in LowerCall_64SVR4()
5136 if (Arg.getValueType() != MVT::f32) { in LowerCall_64SVR4()
5137 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg); in LowerCall_64SVR4()
5141 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg); in LowerCall_64SVR4()
5142 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal); in LowerCall_64SVR4()
5148 Lo = DAG.getNode(ISD::BITCAST, dl, MVT::i32, OutVals[i - 1]); in LowerCall_64SVR4()
5149 Hi = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg); in LowerCall_64SVR4()
5152 ArgVal = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); in LowerCall_64SVR4()
5156 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg); in LowerCall_64SVR4()
5157 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal); in LowerCall_64SVR4()
5159 ArgVal = DAG.getNode(ISD::SHL, dl, MVT::i64, ArgVal, in LowerCall_64SVR4()
5160 DAG.getConstant(32, dl, MVT::i32)); in LowerCall_64SVR4()
5175 if (Arg.getValueType() == MVT::f32 && in LowerCall_64SVR4()
5191 ArgOffset += (Arg.getValueType() == MVT::f32 && in LowerCall_64SVR4()
5198 case MVT::v4f32: in LowerCall_64SVR4()
5199 case MVT::v4i32: in LowerCall_64SVR4()
5200 case MVT::v8i16: in LowerCall_64SVR4()
5201 case MVT::v16i8: in LowerCall_64SVR4()
5202 case MVT::v2f64: in LowerCall_64SVR4()
5203 case MVT::v2i64: in LowerCall_64SVR4()
5204 case MVT::v1i128: in LowerCall_64SVR4()
5221 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff, in LowerCall_64SVR4()
5226 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 || in LowerCall_64SVR4()
5227 Arg.getSimpleValueType() == MVT::v2i64) ? in LowerCall_64SVR4()
5249 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 || in LowerCall_64SVR4()
5250 Arg.getSimpleValueType() == MVT::v2i64) ? in LowerCall_64SVR4()
5271 assert(Arg.getValueType().getSimpleVT().SimpleTy == MVT::v4f32 && in LowerCall_64SVR4()
5275 case MVT::v4f64: in LowerCall_64SVR4()
5276 case MVT::v4i1: { in LowerCall_64SVR4()
5277 bool IsF32 = Arg.getValueType().getSimpleVT().SimpleTy == MVT::v4f32; in LowerCall_64SVR4()
5285 SDValue Load = DAG.getLoad(IsF32 ? MVT::v4f32 : MVT::v4f64, dl, in LowerCall_64SVR4()
5330 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains); in LowerCall_64SVR4()
5340 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64); in LowerCall_64SVR4()
5388 bool isPPC64 = PtrVT == MVT::i64; in LowerCall_Darwin()
5419 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 || in LowerCall_Darwin()
5420 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 || in LowerCall_Darwin()
5421 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64) { in LowerCall_Darwin()
5478 StackPtr = DAG.getRegister(PPC::X1, MVT::i64); in LowerCall_Darwin()
5480 StackPtr = DAG.getRegister(PPC::R1, MVT::i32); in LowerCall_Darwin()
5524 if (isPPC64 && Arg.getValueType() == MVT::i32) { in LowerCall_Darwin()
5527 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg); in LowerCall_Darwin()
5538 EVT VT = (Size==1) ? MVT::i8 : MVT::i16; in LowerCall_Darwin()
5588 case MVT::i1: in LowerCall_Darwin()
5589 case MVT::i32: in LowerCall_Darwin()
5590 case MVT::i64: in LowerCall_Darwin()
5592 if (Arg.getValueType() == MVT::i1) in LowerCall_Darwin()
5603 case MVT::f32: in LowerCall_Darwin()
5604 case MVT::f64: in LowerCall_Darwin()
5621 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){ in LowerCall_Darwin()
5636 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && in LowerCall_Darwin()
5647 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8; in LowerCall_Darwin()
5649 case MVT::v4f32: in LowerCall_Darwin()
5650 case MVT::v4i32: in LowerCall_Darwin()
5651 case MVT::v8i16: in LowerCall_Darwin()
5652 case MVT::v16i8: in LowerCall_Darwin()
5672 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff, in LowerCall_Darwin()
5720 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 || in LowerCall_Darwin()
5721 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) { in LowerCall_Darwin()
5735 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains); in LowerCall_Darwin()
5823 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, RetOps); in LowerReturn()
5934 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other); in LowerDYNAMIC_STACKALLOC()
5942 DAG.getVTList(MVT::i32, MVT::Other), in lowerEH_SJLJ_SETJMP()
5949 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other, in lowerEH_SJLJ_LONGJMP()
5957 assert(Op.getValueType() == MVT::i1 && in LowerLOAD()
5971 BasePtr, MVT::i8, MMO); in LowerLOAD()
5972 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewLD); in LowerLOAD()
5982 assert(Op.getOperand(1).getValueType() == MVT::i1 && in LowerSTORE()
5997 return DAG.getTruncStore(Chain, dl, Value, BasePtr, MVT::i8, MMO); in LowerSTORE()
6002 assert(Op.getValueType() == MVT::i1 && in LowerTRUNCATE()
6006 return DAG.getNode(PPCISD::ANDIo_1_GT_BIT, DL, MVT::i1, in LowerTRUNCATE()
6046 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits in LowerSELECT_CC()
6047 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); in LowerSELECT_CC()
6049 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits in LowerSELECT_CC()
6050 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1); in LowerSELECT_CC()
6052 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV); in LowerSELECT_CC()
6058 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits in LowerSELECT_CC()
6059 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); in LowerSELECT_CC()
6066 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits in LowerSELECT_CC()
6067 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); in LowerSELECT_CC()
6069 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV); in LowerSELECT_CC()
6079 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits in LowerSELECT_CC()
6080 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); in LowerSELECT_CC()
6082 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits in LowerSELECT_CC()
6083 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1); in LowerSELECT_CC()
6085 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV); in LowerSELECT_CC()
6089 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits in LowerSELECT_CC()
6090 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); in LowerSELECT_CC()
6095 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits in LowerSELECT_CC()
6096 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); in LowerSELECT_CC()
6101 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits in LowerSELECT_CC()
6102 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); in LowerSELECT_CC()
6107 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits in LowerSELECT_CC()
6108 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); in LowerSELECT_CC()
6119 if (Src.getValueType() == MVT::f32) in LowerFP_TO_INTForReuse()
6120 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src); in LowerFP_TO_INTForReuse()
6125 case MVT::i32: in LowerFP_TO_INTForReuse()
6130 dl, MVT::f64, Src); in LowerFP_TO_INTForReuse()
6132 case MVT::i64: in LowerFP_TO_INTForReuse()
6137 dl, MVT::f64, Src); in LowerFP_TO_INTForReuse()
6142 bool i32Stack = Op.getValueType() == MVT::i32 && Subtarget.hasSTFIWX() && in LowerFP_TO_INTForReuse()
6144 SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64); in LowerFP_TO_INTForReuse()
6157 DAG.getVTList(MVT::Other), Ops, MVT::i32, MMO); in LowerFP_TO_INTForReuse()
6164 if (Op.getValueType() == MVT::i32 && !i32Stack) { in LowerFP_TO_INTForReuse()
6184 if (Src.getValueType() == MVT::f32) in LowerFP_TO_INTDirectMove()
6185 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src); in LowerFP_TO_INTDirectMove()
6190 case MVT::i32: in LowerFP_TO_INTDirectMove()
6195 dl, MVT::f64, Src); in LowerFP_TO_INTDirectMove()
6196 Tmp = DAG.getNode(PPCISD::MFVSR, dl, MVT::i32, Tmp); in LowerFP_TO_INTDirectMove()
6198 case MVT::i64: in LowerFP_TO_INTDirectMove()
6203 dl, MVT::f64, Src); in LowerFP_TO_INTDirectMove()
6204 Tmp = DAG.getNode(PPCISD::MFVSR, dl, MVT::i64, Tmp); in LowerFP_TO_INTDirectMove()
6283 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, in spliceIntoChain()
6284 NewResChain, DAG.getUNDEF(MVT::Other)); in spliceIntoChain()
6298 assert((Op.getValueType() == MVT::f32 || in LowerINT_TO_FPDirectMove()
6299 Op.getValueType() == MVT::f64) && in LowerINT_TO_FPDirectMove()
6305 bool SinglePrec = Op.getValueType() == MVT::f32; in LowerINT_TO_FPDirectMove()
6306 bool WordInt = Src.getSimpleValueType().SimpleTy == MVT::i32; in LowerINT_TO_FPDirectMove()
6313 dl, MVT::f64, Src); in LowerINT_TO_FPDirectMove()
6314 FP = DAG.getNode(ConvOp, dl, SinglePrec ? MVT::f32 : MVT::f64, FP); in LowerINT_TO_FPDirectMove()
6317 FP = DAG.getNode(PPCISD::MTVSRA, dl, MVT::f64, Src); in LowerINT_TO_FPDirectMove()
6318 FP = DAG.getNode(ConvOp, dl, SinglePrec ? MVT::f32 : MVT::f64, FP); in LowerINT_TO_FPDirectMove()
6328 if (Subtarget.hasQPX() && Op.getOperand(0).getValueType() == MVT::v4i1) { in LowerINT_TO_FP()
6329 if (Op.getValueType() != MVT::v4f32 && Op.getValueType() != MVT::v4f64) in LowerINT_TO_FP()
6336 Value = DAG.getNode(PPCISD::QBFLT, dl, MVT::v4f64, Value); in LowerINT_TO_FP()
6338 SDValue FPHalfs = DAG.getConstantFP(0.5, dl, MVT::f64); in LowerINT_TO_FP()
6339 FPHalfs = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f64, FPHalfs, FPHalfs, in LowerINT_TO_FP()
6342 Value = DAG.getNode(ISD::FMA, dl, MVT::v4f64, Value, FPHalfs, FPHalfs); in LowerINT_TO_FP()
6344 if (Op.getValueType() != MVT::v4f64) in LowerINT_TO_FP()
6352 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64) in LowerINT_TO_FP()
6355 if (Op.getOperand(0).getValueType() == MVT::i1) in LowerINT_TO_FP()
6370 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) in LowerINT_TO_FP()
6375 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) in LowerINT_TO_FP()
6376 ? MVT::f32 in LowerINT_TO_FP()
6377 : MVT::f64; in LowerINT_TO_FP()
6379 if (Op.getOperand(0).getValueType() == MVT::i64) { in LowerINT_TO_FP()
6391 if (Op.getValueType() == MVT::f32 && in LowerINT_TO_FP()
6401 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64, in LowerINT_TO_FP()
6402 SINT, DAG.getConstant(2047, dl, MVT::i64)); in LowerINT_TO_FP()
6403 Round = DAG.getNode(ISD::ADD, dl, MVT::i64, in LowerINT_TO_FP()
6404 Round, DAG.getConstant(2047, dl, MVT::i64)); in LowerINT_TO_FP()
6405 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT); in LowerINT_TO_FP()
6406 Round = DAG.getNode(ISD::AND, dl, MVT::i64, in LowerINT_TO_FP()
6407 Round, DAG.getConstant(-2048, dl, MVT::i64)); in LowerINT_TO_FP()
6417 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64, in LowerINT_TO_FP()
6418 SINT, DAG.getConstant(53, dl, MVT::i32)); in LowerINT_TO_FP()
6419 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64, in LowerINT_TO_FP()
6420 Cond, DAG.getConstant(1, dl, MVT::i64)); in LowerINT_TO_FP()
6421 Cond = DAG.getSetCC(dl, MVT::i32, in LowerINT_TO_FP()
6422 Cond, DAG.getConstant(1, dl, MVT::i64), ISD::SETUGT); in LowerINT_TO_FP()
6424 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT); in LowerINT_TO_FP()
6431 if (canReuseLoadAddress(SINT, MVT::i64, RLI, DAG)) { in LowerINT_TO_FP()
6432 Bits = DAG.getLoad(MVT::f64, dl, RLI.Chain, RLI.Ptr, RLI.MPI, false, in LowerINT_TO_FP()
6437 canReuseLoadAddress(SINT, MVT::i32, RLI, DAG, ISD::SEXTLOAD)) { in LowerINT_TO_FP()
6443 DAG.getVTList(MVT::f64, MVT::Other), in LowerINT_TO_FP()
6444 Ops, MVT::i32, MMO); in LowerINT_TO_FP()
6447 canReuseLoadAddress(SINT, MVT::i32, RLI, DAG, ISD::ZEXTLOAD)) { in LowerINT_TO_FP()
6453 DAG.getVTList(MVT::f64, MVT::Other), in LowerINT_TO_FP()
6454 Ops, MVT::i32, MMO); in LowerINT_TO_FP()
6460 SINT.getOperand(0).getValueType() == MVT::i32) { in LowerINT_TO_FP()
6472 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 && in LowerINT_TO_FP()
6487 dl, DAG.getVTList(MVT::f64, MVT::Other), in LowerINT_TO_FP()
6488 Ops, MVT::i32, MMO); in LowerINT_TO_FP()
6490 Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT); in LowerINT_TO_FP()
6494 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT()) in LowerINT_TO_FP()
6496 MVT::f32, FP, DAG.getIntPtrConstant(0, dl)); in LowerINT_TO_FP()
6500 assert(Op.getOperand(0).getValueType() == MVT::i32 && in LowerINT_TO_FP()
6514 if (!(ReusingLoad = canReuseLoadAddress(Op.getOperand(0), MVT::i32, RLI, in LowerINT_TO_FP()
6524 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 && in LowerINT_TO_FP()
6540 dl, DAG.getVTList(MVT::f64, MVT::Other), in LowerINT_TO_FP()
6541 Ops, MVT::i32, MMO); in LowerINT_TO_FP()
6551 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64, in LowerINT_TO_FP()
6562 MVT::f64, dl, Store, FIdx, in LowerINT_TO_FP()
6569 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT()) in LowerINT_TO_FP()
6570 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, in LowerINT_TO_FP()
6603 MVT::f64, // return register in LowerFLT_ROUNDS_()
6604 MVT::Glue // unused in this context in LowerFLT_ROUNDS_()
6617 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(), in LowerFLT_ROUNDS_()
6622 DAG.getNode(ISD::AND, dl, MVT::i32, in LowerFLT_ROUNDS_()
6623 CWD, DAG.getConstant(3, dl, MVT::i32)); in LowerFLT_ROUNDS_()
6625 DAG.getNode(ISD::SRL, dl, MVT::i32, in LowerFLT_ROUNDS_()
6626 DAG.getNode(ISD::AND, dl, MVT::i32, in LowerFLT_ROUNDS_()
6627 DAG.getNode(ISD::XOR, dl, MVT::i32, in LowerFLT_ROUNDS_()
6628 CWD, DAG.getConstant(3, dl, MVT::i32)), in LowerFLT_ROUNDS_()
6629 DAG.getConstant(3, dl, MVT::i32)), in LowerFLT_ROUNDS_()
6630 DAG.getConstant(1, dl, MVT::i32)); in LowerFLT_ROUNDS_()
6633 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2); in LowerFLT_ROUNDS_()
6736 static const MVT VTys[] = { // canonical VT to use for each size. in BuildSplatI()
6737 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32 in BuildSplatI()
6740 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1]; in BuildSplatI()
6749 SDValue Elt = DAG.getConstant(Val, dl, MVT::i32); in BuildSplatI()
6760 EVT DestVT = MVT::Other) { in BuildIntrinsicOp()
6761 if (DestVT == MVT::Other) DestVT = Op.getValueType(); in BuildIntrinsicOp()
6763 DAG.getConstant(IID, dl, MVT::i32), Op); in BuildIntrinsicOp()
6770 EVT DestVT = MVT::Other) { in BuildIntrinsicOp()
6771 if (DestVT == MVT::Other) DestVT = LHS.getValueType(); in BuildIntrinsicOp()
6773 DAG.getConstant(IID, dl, MVT::i32), LHS, RHS); in BuildIntrinsicOp()
6780 SDLoc dl, EVT DestVT = MVT::Other) { in BuildIntrinsicOp()
6781 if (DestVT == MVT::Other) DestVT = Op0.getValueType(); in BuildIntrinsicOp()
6783 DAG.getConstant(IID, dl, MVT::i32), Op0, Op1, Op2); in BuildIntrinsicOp()
6791 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS); in BuildVSLDOI()
6792 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS); in BuildVSLDOI()
6797 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops); in BuildVSLDOI()
6812 if (Subtarget.hasQPX() && Op.getValueType() == MVT::v4i1) { in LowerBUILD_VECTOR()
6860 ValueVTs.push_back(MVT::v4i1); in LowerBUILD_VECTOR()
6861 ValueVTs.push_back(MVT::Other); // chain in LowerBUILD_VECTOR()
6865 PPCISD::QVLFSb, dl, VTs, Ops, MVT::v4f32, in LowerBUILD_VECTOR()
6882 MVT::i32, false, false, 0)); in LowerBUILD_VECTOR()
6886 StoreValue = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, StoreValue); in LowerBUILD_VECTOR()
6897 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores); in LowerBUILD_VECTOR()
6908 Ops.push_back(DAG.getConstant(Intrinsic::ppc_qpx_qvlfiwz, dl, MVT::i32)); in LowerBUILD_VECTOR()
6912 ValueVTs.push_back(MVT::v4f64); in LowerBUILD_VECTOR()
6913 ValueVTs.push_back(MVT::Other); // chain in LowerBUILD_VECTOR()
6917 dl, VTs, Ops, MVT::v4i32, PtrInfo); in LowerBUILD_VECTOR()
6918 LoadedVect = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f64, in LowerBUILD_VECTOR()
6919 DAG.getConstant(Intrinsic::ppc_qpx_qvfcfidu, dl, MVT::i32), in LowerBUILD_VECTOR()
6922 SDValue FPZeros = DAG.getConstantFP(0.0, dl, MVT::f64); in LowerBUILD_VECTOR()
6923 FPZeros = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f64, in LowerBUILD_VECTOR()
6926 return DAG.getSetCC(dl, MVT::v4i1, LoadedVect, FPZeros, ISD::SETEQ); in LowerBUILD_VECTOR()
6951 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) { in LowerBUILD_VECTOR()
6952 SDValue Z = DAG.getConstant(0, dl, MVT::i32); in LowerBUILD_VECTOR()
6953 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z); in LowerBUILD_VECTOR()
6978 SDValue Elt = DAG.getConstant(SextVal, dl, MVT::i32); in LowerBUILD_VECTOR()
6979 EVT VT = (SplatSize == 1 ? MVT::v16i8 : in LowerBUILD_VECTOR()
6980 (SplatSize == 2 ? MVT::v8i16 : MVT::v4i32)); in LowerBUILD_VECTOR()
6981 SDValue EltSize = DAG.getConstant(SplatSize, dl, MVT::i32); in LowerBUILD_VECTOR()
6994 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl); in LowerBUILD_VECTOR()
7001 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV); in LowerBUILD_VECTOR()
7022 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); in LowerBUILD_VECTOR()
7033 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); in LowerBUILD_VECTOR()
7044 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); in LowerBUILD_VECTOR()
7056 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); in LowerBUILD_VECTOR()
7067 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl); in LowerBUILD_VECTOR()
7073 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl); in LowerBUILD_VECTOR()
7079 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl); in LowerBUILD_VECTOR()
7159 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS); in GeneratePerfectShuffle()
7160 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS); in GeneratePerfectShuffle()
7161 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs); in GeneratePerfectShuffle()
7187 DAG.getConstant(AlignIdx, dl, MVT::i32)); in LowerVECTOR_SHUFFLE()
7199 DAG.getConstant(SplatIdx, dl, MVT::i32)); in LowerVECTOR_SHUFFLE()
7212 SDValue V3 = DAG.getNode(PPCISD::QVGPCI, dl, MVT::v4f64, in LowerVECTOR_SHUFFLE()
7213 DAG.getConstant(idx, dl, MVT::i32)); in LowerVECTOR_SHUFFLE()
7337 dl, MVT::i32)); in LowerVECTOR_SHUFFLE()
7340 MVT::i32)); in LowerVECTOR_SHUFFLE()
7343 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8, in LowerVECTOR_SHUFFLE()
7483 DAG.getConstant(CompareOpc, dl, MVT::i32)); in LowerINTRINSIC_WO_CHAIN()
7491 DAG.getConstant(CompareOpc, dl, MVT::i32) in LowerINTRINSIC_WO_CHAIN()
7493 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue }; in LowerINTRINSIC_WO_CHAIN()
7498 SDValue Flags = DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32, in LowerINTRINSIC_WO_CHAIN()
7499 DAG.getRegister(PPC::CR6, MVT::i32), in LowerINTRINSIC_WO_CHAIN()
7522 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags, in LowerINTRINSIC_WO_CHAIN()
7523 DAG.getConstant(8 - (3 - BitNo), dl, MVT::i32)); in LowerINTRINSIC_WO_CHAIN()
7525 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags, in LowerINTRINSIC_WO_CHAIN()
7526 DAG.getConstant(1, dl, MVT::i32)); in LowerINTRINSIC_WO_CHAIN()
7530 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags, in LowerINTRINSIC_WO_CHAIN()
7531 DAG.getConstant(1, dl, MVT::i32)); in LowerINTRINSIC_WO_CHAIN()
7541 if (Op.getValueType() == MVT::v2i64) { in LowerSIGN_EXTEND_INREG()
7543 if (ExtVT != MVT::v2i32) { in LowerSIGN_EXTEND_INREG()
7544 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0)); in LowerSIGN_EXTEND_INREG()
7545 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32, Op, in LowerSIGN_EXTEND_INREG()
7548 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Op); in LowerSIGN_EXTEND_INREG()
7549 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v2i64, Op, in LowerSIGN_EXTEND_INREG()
7550 DAG.getValueType(MVT::v2i32)); in LowerSIGN_EXTEND_INREG()
7582 assert(N->getOperand(0).getValueType() == MVT::v4i1 && in LowerEXTRACT_VECTOR_ELT()
7593 Value = DAG.getNode(PPCISD::QBFLT, dl, MVT::v4f64, Value); in LowerEXTRACT_VECTOR_ELT()
7597 SDValue FPHalfs = DAG.getConstantFP(0.5, dl, MVT::f64); in LowerEXTRACT_VECTOR_ELT()
7598 FPHalfs = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f64, in LowerEXTRACT_VECTOR_ELT()
7601 Value = DAG.getNode(ISD::FMA, dl, MVT::v4f64, Value, FPHalfs, FPHalfs); in LowerEXTRACT_VECTOR_ELT()
7604 Value = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f64, in LowerEXTRACT_VECTOR_ELT()
7605 DAG.getConstant(Intrinsic::ppc_qpx_qvfctiwu, dl, MVT::i32), in LowerEXTRACT_VECTOR_ELT()
7618 Ops.push_back(DAG.getConstant(Intrinsic::ppc_qpx_qvstfiw, dl, MVT::i32)); in LowerEXTRACT_VECTOR_ELT()
7623 ValueVTs.push_back(MVT::Other); // chain in LowerEXTRACT_VECTOR_ELT()
7627 dl, VTs, Ops, MVT::v4i32, PtrInfo); in LowerEXTRACT_VECTOR_ELT()
7634 SDValue IntVal = DAG.getLoad(MVT::i32, dl, StoreChain, Idx, in LowerEXTRACT_VECTOR_ELT()
7641 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, IntVal); in LowerEXTRACT_VECTOR_ELT()
7652 if (Op.getValueType() == MVT::v4f64 || in LowerVectorLoad()
7653 Op.getValueType() == MVT::v4f32) { in LowerVectorLoad()
7699 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains); in LowerVectorLoad()
7712 assert(Op.getValueType() == MVT::v4i1 && "Unknown load to lower"); in LowerVectorLoad()
7724 dl, MVT::i32, LoadChain, Idx, in LowerVectorLoad()
7726 MVT::i8 /* memory type */, in LowerVectorLoad()
7733 LoadChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, VectElmtChains); in LowerVectorLoad()
7734 SDValue Value = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i1, VectElmts); in LowerVectorLoad()
7749 if (Value.getValueType() == MVT::v4f64 || in LowerVectorStore()
7750 Value.getValueType() == MVT::v4f32) { in LowerVectorStore()
7794 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores); in LowerVectorStore()
7805 assert(Value.getValueType() == MVT::v4i1 && "Unknown store to lower"); in LowerVectorStore()
7810 Value = DAG.getNode(PPCISD::QBFLT, dl, MVT::v4f64, Value); in LowerVectorStore()
7814 SDValue FPHalfs = DAG.getConstantFP(0.5, dl, MVT::f64); in LowerVectorStore()
7815 FPHalfs = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f64, in LowerVectorStore()
7818 Value = DAG.getNode(ISD::FMA, dl, MVT::v4f64, Value, FPHalfs, FPHalfs); in LowerVectorStore()
7821 Value = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f64, in LowerVectorStore()
7822 DAG.getConstant(Intrinsic::ppc_qpx_qvfctiwu, dl, MVT::i32), in LowerVectorStore()
7834 Ops.push_back(DAG.getConstant(Intrinsic::ppc_qpx_qvstfiw, dl, MVT::i32)); in LowerVectorStore()
7839 ValueVTs.push_back(MVT::Other); // chain in LowerVectorStore()
7843 dl, VTs, Ops, MVT::v4i32, PtrInfo); in LowerVectorStore()
7852 Loads.push_back(DAG.getLoad(MVT::i32, dl, StoreChain, Idx, in LowerVectorStore()
7858 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains); in LowerVectorStore()
7867 MVT::i8 /* memory type */, SN->isNonTemporal(), SN->isVolatile(), in LowerVectorStore()
7871 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores); in LowerVectorStore()
7878 if (Op.getValueType() == MVT::v4i32) { in LowerMUL()
7881 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl); in LowerMUL()
7882 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt. in LowerMUL()
7888 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS); in LowerMUL()
7889 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS); in LowerMUL()
7890 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap); in LowerMUL()
7895 LHS, RHS, DAG, dl, MVT::v4i32); in LowerMUL()
7898 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32); in LowerMUL()
7902 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd); in LowerMUL()
7903 } else if (Op.getValueType() == MVT::v8i16) { in LowerMUL()
7906 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl); in LowerMUL()
7910 } else if (Op.getValueType() == MVT::v16i8) { in LowerMUL()
7916 LHS, RHS, DAG, dl, MVT::v8i16); in LowerMUL()
7917 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts); in LowerMUL()
7921 LHS, RHS, DAG, dl, MVT::v8i16); in LowerMUL()
7922 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts); in LowerMUL()
7939 return DAG.getVectorShuffle(MVT::v16i8, dl, OddParts, EvenParts, Ops); in LowerMUL()
7941 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops); in LowerMUL()
8019 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other); in ReplaceNodeResults()
8032 assert(N->getValueType(0) == MVT::i1 && in ReplaceNodeResults()
8036 SDVTList VTs = DAG.getVTList(SVT, MVT::Other); in ReplaceNodeResults()
8050 if (VT == MVT::i64) { in ReplaceNodeResults()
8059 assert(N->getValueType(0) == MVT::ppcf128); in ReplaceNodeResults()
8060 assert(N->getOperand(0).getValueType() == MVT::ppcf128); in ReplaceNodeResults()
8062 MVT::f64, N->getOperand(0), in ReplaceNodeResults()
8065 MVT::f64, N->getOperand(0), in ReplaceNodeResults()
8069 SDValue FPreg = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi); in ReplaceNodeResults()
8073 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128, in ReplaceNodeResults()
8080 if (N->getOperand(0).getValueType() == MVT::ppcf128) in ReplaceNodeResults()
8355 assert(RC->hasType(MVT::i32) && "Invalid destination!"); in emitEHSjLjSetJmp()
8359 MVT PVT = getPointerTy(MF->getDataLayout()); in emitEHSjLjSetJmp()
8360 assert((PVT == MVT::i64 || PVT == MVT::i32) && in emitEHSjLjSetJmp()
8497 MVT PVT = getPointerTy(MF->getDataLayout()); in emitEHSjLjLongJmp()
8498 assert((PVT == MVT::i64 || PVT == MVT::i32) && in emitEHSjLjLongJmp()
8502 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass; in emitEHSjLjLongJmp()
8505 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31; in emitEHSjLjLongJmp()
8506 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1; in emitEHSjLjLongJmp()
8508 (PVT == MVT::i64) in emitEHSjLjLongJmp()
8527 if (PVT == MVT::i64) { in emitEHSjLjLongJmp()
8539 if (PVT == MVT::i64) { in emitEHSjLjLongJmp()
8551 if (PVT == MVT::i64) { in emitEHSjLjLongJmp()
8563 if (PVT == MVT::i64) { in emitEHSjLjLongJmp()
8575 if (PVT == MVT::i64 && Subtarget.isSVR4ABI()) { in emitEHSjLjLongJmp()
8586 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp); in emitEHSjLjLongJmp()
8587 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR)); in emitEHSjLjLongJmp()
9144 if (VT.getScalarType() == MVT::f64) in getRecipOp()
9160 if ((VT == MVT::f32 && Subtarget.hasFRSQRTES()) || in getRsqrtEstimate()
9161 (VT == MVT::f64 && Subtarget.hasFRSQRTE()) || in getRsqrtEstimate()
9162 (VT == MVT::v4f32 && Subtarget.hasAltivec()) || in getRsqrtEstimate()
9163 (VT == MVT::v2f64 && Subtarget.hasVSX()) || in getRsqrtEstimate()
9164 (VT == MVT::v4f32 && Subtarget.hasQPX()) || in getRsqrtEstimate()
9165 (VT == MVT::v4f64 && Subtarget.hasQPX())) { in getRsqrtEstimate()
9182 if ((VT == MVT::f32 && Subtarget.hasFRES()) || in getRecipEstimate()
9183 (VT == MVT::f64 && Subtarget.hasFRE()) || in getRecipEstimate()
9184 (VT == MVT::v4f32 && Subtarget.hasAltivec()) || in getRecipEstimate()
9185 (VT == MVT::v2f64 && Subtarget.hasVSX()) || in getRecipEstimate()
9186 (VT == MVT::v4f32 && Subtarget.hasQPX()) || in getRecipEstimate()
9187 (VT == MVT::v4f64 && Subtarget.hasQPX())) { in getRecipEstimate()
9290 VT = MVT::v4f64; in isConsecutiveLS()
9294 VT = MVT::v4f32; in isConsecutiveLS()
9298 VT = MVT::v2f64; in isConsecutiveLS()
9302 VT = MVT::v2f32; in isConsecutiveLS()
9309 VT = MVT::v4i32; in isConsecutiveLS()
9312 VT = MVT::v2f64; in isConsecutiveLS()
9315 VT = MVT::i8; in isConsecutiveLS()
9318 VT = MVT::i16; in isConsecutiveLS()
9321 VT = MVT::i32; in isConsecutiveLS()
9334 VT = MVT::v4f64; in isConsecutiveLS()
9338 VT = MVT::v4f32; in isConsecutiveLS()
9342 VT = MVT::v2f64; in isConsecutiveLS()
9346 VT = MVT::v2f32; in isConsecutiveLS()
9353 VT = MVT::v4i32; in isConsecutiveLS()
9356 VT = MVT::v2f64; in isConsecutiveLS()
9359 VT = MVT::i8; in isConsecutiveLS()
9362 VT = MVT::i16; in isConsecutiveLS()
9365 VT = MVT::i32; in isConsecutiveLS()
9459 N->getValueType(0) != MVT::i1) in DAGCombineTruncBoolExt()
9462 if (N->getOperand(0).getValueType() != MVT::i32 && in DAGCombineTruncBoolExt()
9463 N->getOperand(0).getValueType() != MVT::i64) in DAGCombineTruncBoolExt()
9537 N->getOperand(i).getOperand(0).getValueType() == MVT::i1) || in DAGCombineTruncBoolExt()
9568 BinOp.getOperand(i).getOperand(0).getValueType() == MVT::i1) || in DAGCombineTruncBoolExt()
9667 PromOp.getOperand(0).getValueType() != MVT::i1) { in DAGCombineTruncBoolExt()
9675 RepValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, RepValue); in DAGCombineTruncBoolExt()
9689 PromOp.getOperand(C).getValueType() != MVT::i1) || in DAGCombineTruncBoolExt()
9691 PromOp.getOperand(C+1).getValueType() != MVT::i1)) { in DAGCombineTruncBoolExt()
9706 Ops[C+i] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ops[C+i]); in DAGCombineTruncBoolExt()
9709 DAG.getNode(PromOp.getOpcode(), dl, MVT::i1, Ops)); in DAGCombineTruncBoolExt()
9740 if (N->getValueType(0) != MVT::i32 && in DAGCombineExtBoolTrunc()
9741 N->getValueType(0) != MVT::i64) in DAGCombineExtBoolTrunc()
9744 if (!((N->getOperand(0).getValueType() == MVT::i1 && Subtarget.useCRBits()) || in DAGCombineExtBoolTrunc()
9745 (N->getOperand(0).getValueType() == MVT::i32 && Subtarget.isPPC64()))) in DAGCombineExtBoolTrunc()
10014 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64) in combineFPToIntToFP()
10016 if (Op.getOperand(0).getValueType() == MVT::i1) in combineFPToIntToFP()
10023 if (Op.getOperand(0).getValueType() == MVT::i32) in combineFPToIntToFP()
10031 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) in combineFPToIntToFP()
10036 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) in combineFPToIntToFP()
10037 ? MVT::f32 in combineFPToIntToFP()
10038 : MVT::f64; in combineFPToIntToFP()
10046 if (Src.getValueType() == MVT::f32) { in combineFPToIntToFP()
10047 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src); in combineFPToIntToFP()
10049 } else if (Src.getValueType() != MVT::f64) { in combineFPToIntToFP()
10058 SDValue Tmp = DAG.getNode(FCTOp, dl, MVT::f64, Src); in combineFPToIntToFP()
10061 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT()) { in combineFPToIntToFP()
10063 MVT::f32, FP, DAG.getIntPtrConstant(0, dl)); in combineFPToIntToFP()
10109 MVT VecTy = N->getValueType(0).getSimpleVT(); in expandVSXLoadForLE()
10112 DAG.getVTList(VecTy, MVT::Other), in expandVSXLoadForLE()
10117 DAG.getVTList(VecTy, MVT::Other), Chain, Load); in expandVSXLoadForLE()
10161 MVT VecTy = Src.getValueType().getSimpleVT(); in expandVSXStoreForLE()
10163 DAG.getVTList(VecTy, MVT::Other), Chain, Src); in expandVSXStoreForLE()
10168 DAG.getVTList(MVT::Other), in expandVSXStoreForLE()
10210 N->getOperand(1).getValueType() == MVT::i32 && in PerformDAGCombine()
10211 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) { in PerformDAGCombine()
10213 if (Val.getValueType() == MVT::f32) { in PerformDAGCombine()
10214 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val); in PerformDAGCombine()
10217 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val); in PerformDAGCombine()
10226 DAG.getVTList(MVT::Other), Ops, in PerformDAGCombine()
10237 (N->getOperand(1).getValueType() == MVT::i32 || in PerformDAGCombine()
10238 N->getOperand(1).getValueType() == MVT::i16 || in PerformDAGCombine()
10240 N->getOperand(1).getValueType() == MVT::i64))) { in PerformDAGCombine()
10243 if (BSwapOp.getValueType() == MVT::i16) in PerformDAGCombine()
10244 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp); in PerformDAGCombine()
10251 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other), in PerformDAGCombine()
10259 MVT StoreVT = VT.getSimpleVT(); in PerformDAGCombine()
10261 (StoreVT == MVT::v2f64 || StoreVT == MVT::v2i64 || in PerformDAGCombine()
10262 StoreVT == MVT::v4f32 || StoreVT == MVT::v4i32)) in PerformDAGCombine()
10273 MVT LoadVT = VT.getSimpleVT(); in PerformDAGCombine()
10275 (LoadVT == MVT::v2f64 || LoadVT == MVT::v2i64 || in PerformDAGCombine()
10276 LoadVT == MVT::v4f32 || LoadVT == MVT::v4i32)) in PerformDAGCombine()
10288 !Subtarget.hasP8Vector() && (VT == MVT::v16i8 || VT == MVT::v8i16 || in PerformDAGCombine()
10289 VT == MVT::v4i32 || VT == MVT::v4f32)) || in PerformDAGCombine()
10290 (Subtarget.hasQPX() && (VT == MVT::v4f64 || VT == MVT::v4f32) && in PerformDAGCombine()
10323 MVT PermCntlTy, PermTy, LDTy; in PerformDAGCombine()
10329 PermCntlTy = MVT::v16i8; in PerformDAGCombine()
10330 PermTy = MVT::v4i32; in PerformDAGCombine()
10331 LDTy = MVT::v4i32; in PerformDAGCombine()
10333 Intr = MemVT == MVT::v4f64 ? Intrinsic::ppc_qpx_qvlpcld : in PerformDAGCombine()
10335 IntrLD = MemVT == MVT::v4f64 ? Intrinsic::ppc_qpx_qvlfd : in PerformDAGCombine()
10338 PermCntlTy = MVT::v4f64; in PerformDAGCombine()
10339 PermTy = MVT::v4f64; in PerformDAGCombine()
10362 DAG.getVTList(PermTy, MVT::Other), in PerformDAGCombine()
10392 DAG.getVTList(PermTy, MVT::Other), in PerformDAGCombine()
10395 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, in PerformDAGCombine()
10415 DAG.getTargetConstant(1, dl, MVT::i64)); in PerformDAGCombine()
10514 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 || in PerformDAGCombine()
10516 N->getValueType(0) == MVT::i64))) { in PerformDAGCombine()
10527 DAG.getVTList(N->getValueType(0) == MVT::i64 ? in PerformDAGCombine()
10528 MVT::i64 : MVT::i32, MVT::Other), in PerformDAGCombine()
10533 if (N->getValueType(0) == MVT::i16) in PerformDAGCombine()
10534 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad); in PerformDAGCombine()
10614 return DAG.getNode(PPCISD::BDNZ, dl, MVT::Other, in PerformDAGCombine()
10654 return DAG.getNode(isBDNZ ? PPCISD::BDNZ : PPCISD::BDZ, dl, MVT::Other, in PerformDAGCombine()
10673 return DAG.getNode(ISD::BR, dl, MVT::Other, in PerformDAGCombine()
10683 DAG.getConstant(CompareOpc, dl, MVT::i32) in PerformDAGCombine()
10685 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue }; in PerformDAGCombine()
10706 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0), in PerformDAGCombine()
10707 DAG.getConstant(CompOpc, dl, MVT::i32), in PerformDAGCombine()
10708 DAG.getRegister(PPC::CR6, MVT::i32), in PerformDAGCombine()
10724 if (VT == MVT::i64 && !Subtarget.isPPC64()) in BuildSDIVPow2()
10726 if ((VT != MVT::i32 && VT != MVT::i64) || in BuildSDIVPow2()
10764 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16) in computeKnownBitsForTargetNode()
10919 MVT VT) const { in getRegForInlineAsmConstraint()
10924 if (VT == MVT::i64 && Subtarget.isPPC64()) in getRegForInlineAsmConstraint()
10928 if (VT == MVT::i64 && Subtarget.isPPC64()) in getRegForInlineAsmConstraint()
10932 if (VT == MVT::f32 || VT == MVT::i32) in getRegForInlineAsmConstraint()
10934 if (VT == MVT::f64 || VT == MVT::i64) in getRegForInlineAsmConstraint()
10936 if (VT == MVT::v4f64 && Subtarget.hasQPX()) in getRegForInlineAsmConstraint()
10938 if (VT == MVT::v4f32 && Subtarget.hasQPX()) in getRegForInlineAsmConstraint()
10942 if (VT == MVT::v4f64 && Subtarget.hasQPX()) in getRegForInlineAsmConstraint()
10944 if (VT == MVT::v4f32 && Subtarget.hasQPX()) in getRegForInlineAsmConstraint()
10958 if (VT == MVT::f32 && Subtarget.hasP8Vector()) in getRegForInlineAsmConstraint()
10973 if (R.first && VT == MVT::i64 && Subtarget.isPPC64() && in getRegForInlineAsmConstraint()
11014 EVT TCVT = MVT::i64; // All constants taken to be 64 bits so that negative in LowerAsmOperandForConstraint()
11126 isPPC64 ? MVT::i64 : MVT::i32); in LowerRETURNADDR()
11148 bool isPPC64 = PtrVT == MVT::i64; in LowerFRAMEADDR()
11174 if ((isPPC64 && VT != MVT::i64 && VT != MVT::i32) || in getRegisterByName()
11175 (!isPPC64 && VT != MVT::i32)) in getRegisterByName()
11178 bool is64Bit = isPPC64 && VT == MVT::i64; in getRegisterByName()
11218 VT = MVT::i8; in getTgtMemIntrinsic()
11221 VT = MVT::i16; in getTgtMemIntrinsic()
11224 VT = MVT::i32; in getTgtMemIntrinsic()
11227 VT = MVT::v2f64; in getTgtMemIntrinsic()
11230 VT = MVT::v4f64; in getTgtMemIntrinsic()
11233 VT = MVT::v4f32; in getTgtMemIntrinsic()
11236 VT = MVT::v2f64; in getTgtMemIntrinsic()
11239 VT = MVT::v2f32; in getTgtMemIntrinsic()
11242 VT = MVT::v4i32; in getTgtMemIntrinsic()
11266 VT = MVT::v4f64; in getTgtMemIntrinsic()
11269 VT = MVT::v4f32; in getTgtMemIntrinsic()
11272 VT = MVT::v2f64; in getTgtMemIntrinsic()
11275 VT = MVT::v2f32; in getTgtMemIntrinsic()
11278 VT = MVT::v4i32; in getTgtMemIntrinsic()
11308 VT = MVT::i8; in getTgtMemIntrinsic()
11311 VT = MVT::i16; in getTgtMemIntrinsic()
11314 VT = MVT::i32; in getTgtMemIntrinsic()
11317 VT = MVT::v2f64; in getTgtMemIntrinsic()
11320 VT = MVT::v4f64; in getTgtMemIntrinsic()
11323 VT = MVT::v4f32; in getTgtMemIntrinsic()
11326 VT = MVT::v2f64; in getTgtMemIntrinsic()
11329 VT = MVT::v2f32; in getTgtMemIntrinsic()
11332 VT = MVT::v4i32; in getTgtMemIntrinsic()
11355 VT = MVT::v4f64; in getTgtMemIntrinsic()
11358 VT = MVT::v4f32; in getTgtMemIntrinsic()
11361 VT = MVT::v2f64; in getTgtMemIntrinsic()
11364 VT = MVT::v2f32; in getTgtMemIntrinsic()
11367 VT = MVT::v4i32; in getTgtMemIntrinsic()
11412 return MVT::v4f64; in getOptimalMemOpType()
11420 return MVT::v4i32; in getOptimalMemOpType()
11424 return MVT::i64; in getOptimalMemOpType()
11427 return MVT::i32; in getOptimalMemOpType()
11463 if ((MemVT == MVT::i1 || MemVT == MVT::i8 || MemVT == MVT::i16 || in isZExtFree()
11464 (Subtarget.isPPC64() && MemVT == MVT::i32)) && in isZExtFree()
11509 if (VT != MVT::v2f64 && VT != MVT::v2i64 && in allowsMisalignedMemoryAccesses()
11510 VT != MVT::v4f32 && VT != MVT::v4i32) in allowsMisalignedMemoryAccesses()
11517 if (VT == MVT::ppcf128) in allowsMisalignedMemoryAccesses()
11533 case MVT::f32: in isFMAFasterThanFMulAndFAdd()
11534 case MVT::f64: in isFMAFasterThanFMulAndFAdd()
11569 if (VT == MVT::v2i64) in shouldExpandBuildVectorWithShuffles()
11573 if (VT == MVT::v4f32 || VT == MVT::v4f64 || VT == MVT::v4i1) in shouldExpandBuildVectorWithShuffles()