2853       switch (ValVT.getSimpleVT().SimpleTy) {  in LowerFormalArguments_32SVR4()
3247     switch (ObjectVT.getSimpleVT().SimpleTy) {  in LowerFormalArguments_64SVR4()
3368       assert(ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 &&  in LowerFormalArguments_64SVR4()
3376       unsigned Sz = ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 ? 16 : 32;  in LowerFormalArguments_64SVR4()
3379         switch (ObjectVT.getSimpleVT().SimpleTy) {  in LowerFormalArguments_64SVR4()
3527       switch(ObjectVT.getSimpleVT().SimpleTy) {  in LowerFormalArguments_Darwin()
3654     switch (ObjectVT.getSimpleVT().SimpleTy) {  in LowerFormalArguments_Darwin()
4821         switch (ArgVT.getSimpleVT().SimpleTy) {  in LowerCall_64SVR4()
5271       assert(Arg.getValueType().getSimpleVT().SimpleTy == MVT::v4f32 &&  in LowerCall_64SVR4()
5277       bool IsF32 = Arg.getValueType().getSimpleVT().SimpleTy == MVT::v4f32;  in LowerCall_64SVR4()
10109   MVT VecTy = N->getValueType(0).getSimpleVT();  in expandVSXLoadForLE()
10161   MVT VecTy = Src.getValueType().getSimpleVT();  in expandVSXStoreForLE()
10259       MVT StoreVT = VT.getSimpleVT();  in PerformDAGCombine()
10273       MVT LoadVT = VT.getSimpleVT();  in PerformDAGCombine()
10340         LDTy = MemVT.getSimpleVT();  in PerformDAGCombine()
11507   if (VT.getSimpleVT().isVector()) {  in allowsMisalignedMemoryAccesses()
11532   switch (VT.getSimpleVT().SimpleTy) {  in isFMAFasterThanFMulAndFAdd()