Lines Matching refs:MVT
39 static bool CC_Sparc_Assign_SRet(unsigned &ValNo, MVT &ValVT, in CC_Sparc_Assign_SRet()
40 MVT &LocVT, CCValAssign::LocInfo &LocInfo, in CC_Sparc_Assign_SRet()
52 static bool CC_Sparc_Assign_Split_64(unsigned &ValNo, MVT &ValVT, in CC_Sparc_Assign_Split_64()
53 MVT &LocVT, CCValAssign::LocInfo &LocInfo, in CC_Sparc_Assign_Split_64()
80 static bool CC_Sparc_Assign_Ret_Split_64(unsigned &ValNo, MVT &ValVT, in CC_Sparc_Assign_Ret_Split_64()
81 MVT &LocVT, CCValAssign::LocInfo &LocInfo, in CC_Sparc_Assign_Ret_Split_64()
104 static bool CC_Sparc64_Full(unsigned &ValNo, MVT &ValVT, in CC_Sparc64_Full()
105 MVT &LocVT, CCValAssign::LocInfo &LocInfo, in CC_Sparc64_Full()
107 assert((LocVT == MVT::f32 || LocVT == MVT::f128 in CC_Sparc64_Full()
112 unsigned size = (LocVT == MVT::f128) ? 16 : 8; in CC_Sparc64_Full()
113 unsigned alignment = (LocVT == MVT::f128) ? 16 : 8; in CC_Sparc64_Full()
117 if (LocVT == MVT::i64 && Offset < 6*8) in CC_Sparc64_Full()
120 else if (LocVT == MVT::f64 && Offset < 16*8) in CC_Sparc64_Full()
123 else if (LocVT == MVT::f32 && Offset < 16*8) in CC_Sparc64_Full()
126 else if (LocVT == MVT::f128 && Offset < 16*8) in CC_Sparc64_Full()
139 if (LocVT == MVT::f32) in CC_Sparc64_Full()
149 static bool CC_Sparc64_Half(unsigned &ValNo, MVT &ValVT, in CC_Sparc64_Half()
150 MVT &LocVT, CCValAssign::LocInfo &LocInfo, in CC_Sparc64_Half()
155 if (LocVT == MVT::f32 && Offset < 16*8) { in CC_Sparc64_Half()
162 if (LocVT == MVT::i32 && Offset < 6*8) { in CC_Sparc64_Half()
165 LocVT = MVT::i64; in CC_Sparc64_Half()
237 assert(VA.getLocVT() == MVT::v2i32); in LowerReturn_32()
241 SDValue Part0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, in LowerReturn_32()
244 SDValue Part1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, in LowerReturn_32()
278 RetOps[1] = DAG.getConstant(RetAddrOffset, DL, MVT::i32); in LowerReturn_32()
284 return DAG.getNode(SPISD::RET_FLAG, DL, MVT::Other, RetOps); in LowerReturn_32()
310 RetOps.push_back(DAG.getConstant(8, DL, MVT::i32)); in LowerReturn_64()
336 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) { in LowerReturn_64()
337 OutVal = DAG.getNode(ISD::SHL, DL, MVT::i64, OutVal, in LowerReturn_64()
338 DAG.getConstant(32, DL, MVT::i32)); in LowerReturn_64()
343 SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, OutVals[i+1]); in LowerReturn_64()
344 OutVal = DAG.getNode(ISD::OR, DL, MVT::i64, OutVal, NV); in LowerReturn_64()
363 return DAG.getNode(SPISD::RET_FLAG, DL, MVT::Other, RetOps); in LowerReturn_64()
414 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); in LowerFormalArguments_32()
415 SDValue Arg = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, in LowerFormalArguments_32()
424 assert(VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2i32); in LowerFormalArguments_32()
428 SDValue HiVal = DAG.getCopyFromReg(Chain, dl, VRegHi, MVT::i32); in LowerFormalArguments_32()
437 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); in LowerFormalArguments_32()
438 LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, in LowerFormalArguments_32()
444 LoVal = DAG.getCopyFromReg(Chain, dl, loReg, MVT::i32); in LowerFormalArguments_32()
451 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal); in LowerFormalArguments_32()
458 SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); in LowerFormalArguments_32()
459 if (VA.getLocVT() == MVT::f32) in LowerFormalArguments_32()
460 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Arg); in LowerFormalArguments_32()
461 else if (VA.getLocVT() != MVT::i32) { in LowerFormalArguments_32()
462 Arg = DAG.getNode(ISD::AssertSext, dl, MVT::i32, Arg, in LowerFormalArguments_32()
476 assert(VA.getValVT() == MVT::f64 || MVT::v2i32); in LowerFormalArguments_32()
494 SDValue HiVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, in LowerFormalArguments_32()
502 SDValue LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr2, in LowerFormalArguments_32()
510 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal); in LowerFormalArguments_32()
521 if (VA.getValVT() == MVT::i32 || VA.getValVT() == MVT::f32) { in LowerFormalArguments_32()
525 } else if (VA.getValVT() == MVT::f128) { in LowerFormalArguments_32()
544 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); in LowerFormalArguments_32()
570 SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), dl, VReg, MVT::i32); in LowerFormalArguments_32()
574 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); in LowerFormalArguments_32()
584 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains); in LowerFormalArguments_32()
623 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) in LowerFormalArguments_64()
625 DAG.getConstant(32, DL, MVT::i32)); in LowerFormalArguments_64()
690 SDValue VArg = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64); in LowerFormalArguments_64()
699 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains); in LowerFormalArguments_64()
778 SDValue SizeNode = DAG.getConstant(Size, dl, MVT::i32); in LowerCall_32()
830 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); in LowerCall_32()
832 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); in LowerCall_32()
841 assert(VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2i32); in LowerCall_32()
847 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); in LowerCall_32()
849 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); in LowerCall_32()
857 if (VA.getLocVT() == MVT::f64) { in LowerCall_32()
865 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::v2i32, Arg); in LowerCall_32()
868 SDValue Part0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, in LowerCall_32()
871 SDValue Part1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, in LowerCall_32()
884 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); in LowerCall_32()
886 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); in LowerCall_32()
894 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); in LowerCall_32()
896 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); in LowerCall_32()
902 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); in LowerCall_32()
913 if (VA.getLocVT() != MVT::f32) { in LowerCall_32()
917 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg); in LowerCall_32()
925 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); in LowerCall_32()
928 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); in LowerCall_32()
937 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains); in LowerCall_32()
959 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32, 0, TF); in LowerCall_32()
961 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32, TF); in LowerCall_32()
964 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); in LowerCall_32()
969 Ops.push_back(DAG.getTargetConstant(SRetArgSize, dl, MVT::i32)); in LowerCall_32()
1068 MVT ValTy = VA.getLocVT(); in fixupVariableFloatArgs()
1071 if (!VA.isRegLoc() || (ValTy != MVT::f64 && ValTy != MVT::f128)) in fixupVariableFloatArgs()
1081 unsigned firstReg = (ValTy == MVT::f64) ? SP::D0 : SP::Q0; in fixupVariableFloatArgs()
1082 unsigned argSize = (ValTy == MVT::f64) ? 8 : 16; in fixupVariableFloatArgs()
1089 if (ValTy == MVT::f64) in fixupVariableFloatArgs()
1092 IReg, MVT::i64, CCValAssign::BCvt); in fixupVariableFloatArgs()
1094 assert(ValTy == MVT::f128 && "Unexpected type!"); in fixupVariableFloatArgs()
1098 IReg, MVT::i128, CCValAssign::BCvt); in fixupVariableFloatArgs()
1178 if (!VA.needsCustom() || VA.getValVT() != MVT::f128 in LowerCall_64()
1179 || VA.getLocVT() != MVT::i128) in LowerCall_64()
1185 if (VA.needsCustom() && VA.getValVT() == MVT::f128 in LowerCall_64()
1186 && VA.getLocVT() == MVT::i128) { in LowerCall_64()
1201 SDValue Hi64 = DAG.getLoad(MVT::i64, DL, Store, HiPtrOff, in LowerCall_64()
1204 SDValue Lo64 = DAG.getLoad(MVT::i64, DL, Store, LoPtrOff, in LowerCall_64()
1216 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) { in LowerCall_64()
1217 Arg = DAG.getNode(ISD::SHL, DL, MVT::i64, Arg, in LowerCall_64()
1218 DAG.getConstant(32, DL, MVT::i32)); in LowerCall_64()
1224 SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, in LowerCall_64()
1226 Arg = DAG.getNode(ISD::OR, DL, MVT::i64, Arg, NV); in LowerCall_64()
1252 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains); in LowerCall_64()
1300 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); in LowerCall_64()
1319 if (CLI.Ins.size() == 1 && CLI.Ins[0].VT == MVT::f32 && CLI.CS == nullptr) in LowerCall_64()
1345 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) in LowerCall_64()
1347 DAG.getConstant(32, DL, MVT::i32)); in LowerCall_64()
1427 MVT PtrVT = MVT::getIntegerVT(8 * TM.getPointerSize()); in SparcTargetLowering()
1438 addRegisterClass(MVT::i32, &SP::IntRegsRegClass); in SparcTargetLowering()
1439 addRegisterClass(MVT::f32, &SP::FPRegsRegClass); in SparcTargetLowering()
1440 addRegisterClass(MVT::f64, &SP::DFPRegsRegClass); in SparcTargetLowering()
1441 addRegisterClass(MVT::f128, &SP::QFPRegsRegClass); in SparcTargetLowering()
1443 addRegisterClass(MVT::i64, &SP::I64RegsRegClass); in SparcTargetLowering()
1447 addRegisterClass(MVT::v2i32, &SP::IntPairRegClass); in SparcTargetLowering()
1452 setOperationAction(Op, MVT::v2i32, Expand); in SparcTargetLowering()
1455 for (MVT VT : MVT::integer_vector_valuetypes()) { in SparcTargetLowering()
1456 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Expand); in SparcTargetLowering()
1457 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i32, Expand); in SparcTargetLowering()
1458 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Expand); in SparcTargetLowering()
1460 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, VT, Expand); in SparcTargetLowering()
1461 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i32, VT, Expand); in SparcTargetLowering()
1462 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, VT, Expand); in SparcTargetLowering()
1464 setTruncStoreAction(VT, MVT::v2i32, Expand); in SparcTargetLowering()
1465 setTruncStoreAction(MVT::v2i32, VT, Expand); in SparcTargetLowering()
1468 setOperationAction(ISD::LOAD, MVT::v2i32, Legal); in SparcTargetLowering()
1469 setOperationAction(ISD::STORE, MVT::v2i32, Legal); in SparcTargetLowering()
1470 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i32, Legal); in SparcTargetLowering()
1471 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Legal); in SparcTargetLowering()
1474 setOperationAction(ISD::LOAD, MVT::i64, Custom); in SparcTargetLowering()
1475 setOperationAction(ISD::STORE, MVT::i64, Custom); in SparcTargetLowering()
1483 for (MVT VT : MVT::fp_valuetypes()) { in SparcTargetLowering()
1484 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand); in SparcTargetLowering()
1485 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f64, Expand); in SparcTargetLowering()
1489 for (MVT VT : MVT::integer_valuetypes()) in SparcTargetLowering()
1490 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in SparcTargetLowering()
1493 setTruncStoreAction(MVT::f64, MVT::f32, Expand); in SparcTargetLowering()
1494 setTruncStoreAction(MVT::f128, MVT::f32, Expand); in SparcTargetLowering()
1495 setTruncStoreAction(MVT::f128, MVT::f64, Expand); in SparcTargetLowering()
1504 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); in SparcTargetLowering()
1505 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); in SparcTargetLowering()
1506 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); in SparcTargetLowering()
1509 setOperationAction(ISD::UREM, MVT::i32, Expand); in SparcTargetLowering()
1510 setOperationAction(ISD::SREM, MVT::i32, Expand); in SparcTargetLowering()
1511 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); in SparcTargetLowering()
1512 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); in SparcTargetLowering()
1516 setOperationAction(ISD::UREM, MVT::i64, Expand); in SparcTargetLowering()
1517 setOperationAction(ISD::SREM, MVT::i64, Expand); in SparcTargetLowering()
1518 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); in SparcTargetLowering()
1519 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); in SparcTargetLowering()
1523 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in SparcTargetLowering()
1524 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); in SparcTargetLowering()
1525 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in SparcTargetLowering()
1526 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); in SparcTargetLowering()
1529 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); in SparcTargetLowering()
1530 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); in SparcTargetLowering()
1531 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom); in SparcTargetLowering()
1532 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom); in SparcTargetLowering()
1534 setOperationAction(ISD::BITCAST, MVT::f32, Expand); in SparcTargetLowering()
1535 setOperationAction(ISD::BITCAST, MVT::i32, Expand); in SparcTargetLowering()
1538 setOperationAction(ISD::SELECT, MVT::i32, Expand); in SparcTargetLowering()
1539 setOperationAction(ISD::SELECT, MVT::f32, Expand); in SparcTargetLowering()
1540 setOperationAction(ISD::SELECT, MVT::f64, Expand); in SparcTargetLowering()
1541 setOperationAction(ISD::SELECT, MVT::f128, Expand); in SparcTargetLowering()
1543 setOperationAction(ISD::SETCC, MVT::i32, Expand); in SparcTargetLowering()
1544 setOperationAction(ISD::SETCC, MVT::f32, Expand); in SparcTargetLowering()
1545 setOperationAction(ISD::SETCC, MVT::f64, Expand); in SparcTargetLowering()
1546 setOperationAction(ISD::SETCC, MVT::f128, Expand); in SparcTargetLowering()
1549 setOperationAction(ISD::BRCOND, MVT::Other, Expand); in SparcTargetLowering()
1550 setOperationAction(ISD::BRIND, MVT::Other, Expand); in SparcTargetLowering()
1551 setOperationAction(ISD::BR_JT, MVT::Other, Expand); in SparcTargetLowering()
1552 setOperationAction(ISD::BR_CC, MVT::i32, Custom); in SparcTargetLowering()
1553 setOperationAction(ISD::BR_CC, MVT::f32, Custom); in SparcTargetLowering()
1554 setOperationAction(ISD::BR_CC, MVT::f64, Custom); in SparcTargetLowering()
1555 setOperationAction(ISD::BR_CC, MVT::f128, Custom); in SparcTargetLowering()
1557 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); in SparcTargetLowering()
1558 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); in SparcTargetLowering()
1559 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); in SparcTargetLowering()
1560 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom); in SparcTargetLowering()
1563 setOperationAction(ISD::ADDC, MVT::i64, Custom); in SparcTargetLowering()
1564 setOperationAction(ISD::ADDE, MVT::i64, Custom); in SparcTargetLowering()
1565 setOperationAction(ISD::SUBC, MVT::i64, Custom); in SparcTargetLowering()
1566 setOperationAction(ISD::SUBE, MVT::i64, Custom); in SparcTargetLowering()
1567 setOperationAction(ISD::BITCAST, MVT::f64, Expand); in SparcTargetLowering()
1568 setOperationAction(ISD::BITCAST, MVT::i64, Expand); in SparcTargetLowering()
1569 setOperationAction(ISD::SELECT, MVT::i64, Expand); in SparcTargetLowering()
1570 setOperationAction(ISD::SETCC, MVT::i64, Expand); in SparcTargetLowering()
1571 setOperationAction(ISD::BR_CC, MVT::i64, Custom); in SparcTargetLowering()
1572 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom); in SparcTargetLowering()
1574 setOperationAction(ISD::CTPOP, MVT::i64, in SparcTargetLowering()
1576 setOperationAction(ISD::CTTZ , MVT::i64, Expand); in SparcTargetLowering()
1577 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand); in SparcTargetLowering()
1578 setOperationAction(ISD::CTLZ , MVT::i64, Expand); in SparcTargetLowering()
1579 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand); in SparcTargetLowering()
1580 setOperationAction(ISD::BSWAP, MVT::i64, Expand); in SparcTargetLowering()
1581 setOperationAction(ISD::ROTL , MVT::i64, Expand); in SparcTargetLowering()
1582 setOperationAction(ISD::ROTR , MVT::i64, Expand); in SparcTargetLowering()
1583 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Custom); in SparcTargetLowering()
1592 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Legal); in SparcTargetLowering()
1593 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, in SparcTargetLowering()
1597 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Legal); in SparcTargetLowering()
1600 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom); in SparcTargetLowering()
1601 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom); in SparcTargetLowering()
1604 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Legal); in SparcTargetLowering()
1605 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Legal); in SparcTargetLowering()
1606 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom); in SparcTargetLowering()
1607 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Custom); in SparcTargetLowering()
1612 setOperationAction(ISD::FNEG, MVT::f64, Custom); in SparcTargetLowering()
1613 setOperationAction(ISD::FABS, MVT::f64, Custom); in SparcTargetLowering()
1616 setOperationAction(ISD::FSIN , MVT::f128, Expand); in SparcTargetLowering()
1617 setOperationAction(ISD::FCOS , MVT::f128, Expand); in SparcTargetLowering()
1618 setOperationAction(ISD::FSINCOS, MVT::f128, Expand); in SparcTargetLowering()
1619 setOperationAction(ISD::FREM , MVT::f128, Expand); in SparcTargetLowering()
1620 setOperationAction(ISD::FMA , MVT::f128, Expand); in SparcTargetLowering()
1621 setOperationAction(ISD::FSIN , MVT::f64, Expand); in SparcTargetLowering()
1622 setOperationAction(ISD::FCOS , MVT::f64, Expand); in SparcTargetLowering()
1623 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); in SparcTargetLowering()
1624 setOperationAction(ISD::FREM , MVT::f64, Expand); in SparcTargetLowering()
1625 setOperationAction(ISD::FMA , MVT::f64, Expand); in SparcTargetLowering()
1626 setOperationAction(ISD::FSIN , MVT::f32, Expand); in SparcTargetLowering()
1627 setOperationAction(ISD::FCOS , MVT::f32, Expand); in SparcTargetLowering()
1628 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); in SparcTargetLowering()
1629 setOperationAction(ISD::FREM , MVT::f32, Expand); in SparcTargetLowering()
1630 setOperationAction(ISD::FMA , MVT::f32, Expand); in SparcTargetLowering()
1631 setOperationAction(ISD::CTTZ , MVT::i32, Expand); in SparcTargetLowering()
1632 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand); in SparcTargetLowering()
1633 setOperationAction(ISD::CTLZ , MVT::i32, Expand); in SparcTargetLowering()
1634 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand); in SparcTargetLowering()
1635 setOperationAction(ISD::ROTL , MVT::i32, Expand); in SparcTargetLowering()
1636 setOperationAction(ISD::ROTR , MVT::i32, Expand); in SparcTargetLowering()
1637 setOperationAction(ISD::BSWAP, MVT::i32, Expand); in SparcTargetLowering()
1638 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand); in SparcTargetLowering()
1639 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); in SparcTargetLowering()
1640 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); in SparcTargetLowering()
1641 setOperationAction(ISD::FPOW , MVT::f128, Expand); in SparcTargetLowering()
1642 setOperationAction(ISD::FPOW , MVT::f64, Expand); in SparcTargetLowering()
1643 setOperationAction(ISD::FPOW , MVT::f32, Expand); in SparcTargetLowering()
1645 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); in SparcTargetLowering()
1646 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); in SparcTargetLowering()
1647 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); in SparcTargetLowering()
1650 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); in SparcTargetLowering()
1651 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); in SparcTargetLowering()
1654 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); in SparcTargetLowering()
1655 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); in SparcTargetLowering()
1656 setOperationAction(ISD::MULHU, MVT::i64, Expand); in SparcTargetLowering()
1657 setOperationAction(ISD::MULHS, MVT::i64, Expand); in SparcTargetLowering()
1659 setOperationAction(ISD::UMULO, MVT::i64, Custom); in SparcTargetLowering()
1660 setOperationAction(ISD::SMULO, MVT::i64, Custom); in SparcTargetLowering()
1662 setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand); in SparcTargetLowering()
1663 setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand); in SparcTargetLowering()
1664 setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand); in SparcTargetLowering()
1668 setOperationAction(ISD::VASTART , MVT::Other, Custom); in SparcTargetLowering()
1670 setOperationAction(ISD::VAARG , MVT::Other, Custom); in SparcTargetLowering()
1672 setOperationAction(ISD::TRAP , MVT::Other, Legal); in SparcTargetLowering()
1675 setOperationAction(ISD::VACOPY , MVT::Other, Expand); in SparcTargetLowering()
1676 setOperationAction(ISD::VAEND , MVT::Other, Expand); in SparcTargetLowering()
1677 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); in SparcTargetLowering()
1678 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand); in SparcTargetLowering()
1679 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); in SparcTargetLowering()
1683 setOperationAction(ISD::CTPOP, MVT::i32, in SparcTargetLowering()
1687 setOperationAction(ISD::LOAD, MVT::f128, Legal); in SparcTargetLowering()
1688 setOperationAction(ISD::STORE, MVT::f128, Legal); in SparcTargetLowering()
1690 setOperationAction(ISD::LOAD, MVT::f128, Custom); in SparcTargetLowering()
1691 setOperationAction(ISD::STORE, MVT::f128, Custom); in SparcTargetLowering()
1695 setOperationAction(ISD::FADD, MVT::f128, Legal); in SparcTargetLowering()
1696 setOperationAction(ISD::FSUB, MVT::f128, Legal); in SparcTargetLowering()
1697 setOperationAction(ISD::FMUL, MVT::f128, Legal); in SparcTargetLowering()
1698 setOperationAction(ISD::FDIV, MVT::f128, Legal); in SparcTargetLowering()
1699 setOperationAction(ISD::FSQRT, MVT::f128, Legal); in SparcTargetLowering()
1700 setOperationAction(ISD::FP_EXTEND, MVT::f128, Legal); in SparcTargetLowering()
1701 setOperationAction(ISD::FP_ROUND, MVT::f64, Legal); in SparcTargetLowering()
1703 setOperationAction(ISD::FNEG, MVT::f128, Legal); in SparcTargetLowering()
1704 setOperationAction(ISD::FABS, MVT::f128, Legal); in SparcTargetLowering()
1706 setOperationAction(ISD::FNEG, MVT::f128, Custom); in SparcTargetLowering()
1707 setOperationAction(ISD::FABS, MVT::f128, Custom); in SparcTargetLowering()
1720 setOperationAction(ISD::FADD, MVT::f128, Custom); in SparcTargetLowering()
1721 setOperationAction(ISD::FSUB, MVT::f128, Custom); in SparcTargetLowering()
1722 setOperationAction(ISD::FMUL, MVT::f128, Custom); in SparcTargetLowering()
1723 setOperationAction(ISD::FDIV, MVT::f128, Custom); in SparcTargetLowering()
1724 setOperationAction(ISD::FSQRT, MVT::f128, Custom); in SparcTargetLowering()
1725 setOperationAction(ISD::FNEG, MVT::f128, Custom); in SparcTargetLowering()
1726 setOperationAction(ISD::FABS, MVT::f128, Custom); in SparcTargetLowering()
1728 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom); in SparcTargetLowering()
1729 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom); in SparcTargetLowering()
1730 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom); in SparcTargetLowering()
1808 return MVT::i32; in getSetCCResultType()
1933 H44 = DAG.getNode(ISD::SHL, DL, VT, H44, DAG.getConstant(12, DL, MVT::i32)); in makeAddress()
1942 Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, DAG.getConstant(32, DL, MVT::i32)); in makeAddress()
2006 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); in LowerGlobalTLSAddress()
2037 unsigned ldTF = ((PtrVT == MVT::i64)? SparcMCExpr::VK_Sparc_TLS_IE_LDX in LowerGlobalTLSAddress()
2207 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); in LowerF128Compare()
2214 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); in LowerF128Compare()
2219 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); in LowerF128Compare()
2224 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); in LowerF128Compare()
2229 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); in LowerF128Compare()
2235 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); in LowerF128Compare()
2240 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); in LowerF128Compare()
2247 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); in LowerF128Compare()
2254 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); in LowerF128Compare()
2263 if (Op.getOperand(0).getValueType() == MVT::f64) in LowerF128_FPEXTEND()
2267 if (Op.getOperand(0).getValueType() == MVT::f32) in LowerF128_FPEXTEND()
2279 if (Op.getOperand(0).getValueType() != MVT::f128) in LowerF128_FPROUND()
2282 if (Op.getValueType() == MVT::f64) in LowerF128_FPROUND()
2285 if (Op.getValueType() == MVT::f32) in LowerF128_FPROUND()
2298 assert(VT == MVT::i32 || VT == MVT::i64); in LowerFP_TO_SINT()
2301 if (Op.getOperand(0).getValueType() == MVT::f128 in LowerFP_TO_SINT()
2303 const char *libName = TLI.getLibcallName(VT == MVT::i32 in LowerFP_TO_SINT()
2314 if (VT == MVT::i32) in LowerFP_TO_SINT()
2315 Op = DAG.getNode(SPISD::FTOI, dl, MVT::f32, Op.getOperand(0)); in LowerFP_TO_SINT()
2317 Op = DAG.getNode(SPISD::FTOX, dl, MVT::f64, Op.getOperand(0)); in LowerFP_TO_SINT()
2327 assert(OpVT == MVT::i32 || (OpVT == MVT::i64)); in LowerSINT_TO_FP()
2329 EVT floatVT = (OpVT == MVT::i32) ? MVT::f32 : MVT::f64; in LowerSINT_TO_FP()
2332 if (Op.getValueType() == MVT::f128 in LowerSINT_TO_FP()
2334 const char *libName = TLI.getLibcallName(OpVT == MVT::i32 in LowerSINT_TO_FP()
2346 unsigned opcode = (OpVT == MVT::i32)? SPISD::ITOF : SPISD::XTOF; in LowerSINT_TO_FP()
2358 if (Op.getOperand(0).getValueType() != MVT::f128 || in LowerFP_TO_UINT()
2362 assert(VT == MVT::i32 || VT == MVT::i64); in LowerFP_TO_UINT()
2365 TLI.getLibcallName(VT == MVT::i32 in LowerFP_TO_UINT()
2376 assert(OpVT == MVT::i32 || OpVT == MVT::i64); in LowerUINT_TO_FP()
2380 if (Op.getValueType() != MVT::f128 || (hasHardQuad && TLI.isTypeLegal(OpVT))) in LowerUINT_TO_FP()
2384 TLI.getLibcallName(OpVT == MVT::i32 in LowerUINT_TO_FP()
2408 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, MVT::Glue, LHS, RHS); in LowerBR_CC()
2411 Opc = LHS.getValueType() == MVT::i32 ? SPISD::BRICC : SPISD::BRXCC; in LowerBR_CC()
2413 if (!hasHardQuad && LHS.getValueType() == MVT::f128) { in LowerBR_CC()
2418 CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS); in LowerBR_CC()
2423 return DAG.getNode(Opc, dl, MVT::Other, Chain, Dest, in LowerBR_CC()
2424 DAG.getConstant(SPCC, dl, MVT::i32), CompareFlag); in LowerBR_CC()
2444 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, MVT::Glue, LHS, RHS); in LowerSELECT_CC()
2445 Opc = LHS.getValueType() == MVT::i32 ? in LowerSELECT_CC()
2449 if (!hasHardQuad && LHS.getValueType() == MVT::f128) { in LowerSELECT_CC()
2454 CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS); in LowerSELECT_CC()
2460 DAG.getConstant(SPCC, dl, MVT::i32), CompareFlag); in LowerSELECT_CC()
2534 dl, MVT::Other, DAG.getEntryNode()); in getFLUSHW()
2626 assert(Op.getValueType() == MVT::f64 && "LowerF64Op called on non-double!"); in LowerF64Op()
2634 SDValue Hi32 = DAG.getTargetExtractSubreg(SP::sub_even, dl, MVT::f32, in LowerF64Op()
2636 SDValue Lo32 = DAG.getTargetExtractSubreg(SP::sub_odd, dl, MVT::f32, in LowerF64Op()
2639 Hi32 = DAG.getNode(opcode, dl, MVT::f32, Hi32); in LowerF64Op()
2642 dl, MVT::f64), 0); in LowerF64Op()
2643 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_even, dl, MVT::f64, in LowerF64Op()
2645 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_odd, dl, MVT::f64, in LowerF64Op()
2662 SDValue Hi64 = DAG.getLoad(MVT::f64, in LowerF128Load()
2672 SDValue Lo64 = DAG.getLoad(MVT::f64, in LowerF128Load()
2679 SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, dl, MVT::i32); in LowerF128Load()
2680 SDValue SubRegOdd = DAG.getTargetConstant(SP::sub_odd64, dl, MVT::i32); in LowerF128Load()
2683 dl, MVT::f128); in LowerF128Load()
2685 MVT::f128, in LowerF128Load()
2690 MVT::f128, in LowerF128Load()
2696 SDValue OutChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains); in LowerF128Load()
2706 if (MemVT == MVT::f128) in LowerLOAD()
2718 SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, dl, MVT::i32); in LowerF128Store()
2719 SDValue SubRegOdd = DAG.getTargetConstant(SP::sub_odd64, dl, MVT::i32); in LowerF128Store()
2723 MVT::f64, in LowerF128Store()
2728 MVT::f64, in LowerF128Store()
2753 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains); in LowerF128Store()
2762 if (MemVT == MVT::f128) in LowerSTORE()
2765 if (MemVT == MVT::i64) { in LowerSTORE()
2768 SDValue Val = DAG.getNode(ISD::BITCAST, dl, MVT::v2i32, St->getValue()); in LowerSTORE()
2783 if (Op.getValueType() == MVT::f64) in LowerFNEGorFABS()
2785 if (Op.getValueType() != MVT::f128) in LowerFNEGorFABS()
2793 SDValue Hi64 = DAG.getTargetExtractSubreg(SP::sub_even64, dl, MVT::f64, in LowerFNEGorFABS()
2795 SDValue Lo64 = DAG.getTargetExtractSubreg(SP::sub_odd64, dl, MVT::f64, in LowerFNEGorFABS()
2798 Hi64 = DAG.getNode(Op.getOpcode(), dl, MVT::f64, Hi64); in LowerFNEGorFABS()
2803 dl, MVT::f128), 0); in LowerFNEGorFABS()
2804 DstReg128 = DAG.getTargetInsertSubreg(SP::sub_even64, dl, MVT::f128, in LowerFNEGorFABS()
2806 DstReg128 = DAG.getTargetInsertSubreg(SP::sub_odd64, dl, MVT::f128, in LowerFNEGorFABS()
2813 if (Op.getValueType() != MVT::i64) in LowerADDC_ADDE_SUBC_SUBE()
2818 SDValue Src1Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1); in LowerADDC_ADDE_SUBC_SUBE()
2819 SDValue Src1Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src1, in LowerADDC_ADDE_SUBC_SUBE()
2820 DAG.getConstant(32, dl, MVT::i64)); in LowerADDC_ADDE_SUBC_SUBE()
2821 Src1Hi = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1Hi); in LowerADDC_ADDE_SUBC_SUBE()
2824 SDValue Src2Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src2); in LowerADDC_ADDE_SUBC_SUBE()
2825 SDValue Src2Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src2, in LowerADDC_ADDE_SUBC_SUBE()
2826 DAG.getConstant(32, dl, MVT::i64)); in LowerADDC_ADDE_SUBC_SUBE()
2827 Src2Hi = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src2Hi); in LowerADDC_ADDE_SUBC_SUBE()
2840 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Glue); in LowerADDC_ADDE_SUBC_SUBE()
2850 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Lo); in LowerADDC_ADDE_SUBC_SUBE()
2851 Hi = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Hi); in LowerADDC_ADDE_SUBC_SUBE()
2852 Hi = DAG.getNode(ISD::SHL, dl, MVT::i64, Hi, in LowerADDC_ADDE_SUBC_SUBE()
2853 DAG.getConstant(32, dl, MVT::i64)); in LowerADDC_ADDE_SUBC_SUBE()
2855 SDValue Dst = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, Lo); in LowerADDC_ADDE_SUBC_SUBE()
2869 EVT VT = MVT::i64; in LowerUMULO_SMULO()
2870 EVT WideVT = MVT::i128; in LowerUMULO_SMULO()
2881 SDValue HiRHS = DAG.getNode(ISD::SRA, dl, MVT::i64, RHS, ShiftAmt); in LowerUMULO_SMULO()
2893 TopHalf = DAG.getSetCC(dl, MVT::i32, TopHalf, Tmp1, ISD::SETNE); in LowerUMULO_SMULO()
2895 TopHalf = DAG.getSetCC(dl, MVT::i32, TopHalf, DAG.getConstant(0, dl, VT), in LowerUMULO_SMULO()
3277 MVT VT) const { in getRegForInlineAsmConstraint()
3281 if (VT == MVT::v2i32) in getRegForInlineAsmConstraint()
3333 if (N->getOperand(0).getValueType() != MVT::f128 in ReplaceNodeResults()
3334 || N->getValueType(0) != MVT::i64) in ReplaceNodeResults()
3349 if (N->getValueType(0) != MVT::f128 in ReplaceNodeResults()
3350 || N->getOperand(0).getValueType() != MVT::i64) in ReplaceNodeResults()
3366 if (Ld->getValueType(0) != MVT::i64 || Ld->getMemoryVT() != MVT::i64) in ReplaceNodeResults()
3371 Ld->getExtensionType(), dl, MVT::v2i32, in ReplaceNodeResults()
3373 MVT::v2i32, Ld->isVolatile(), Ld->isNonTemporal(), in ReplaceNodeResults()
3376 SDValue Res = DAG.getNode(ISD::BITCAST, dl, MVT::i64, LoadRes); in ReplaceNodeResults()