Lines Matching refs:IntRegs
266 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
269 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
304 def LDSTUBrr : F3_1<3, 0b001101, (outs IntRegs:$dst), (ins MEMrr:$addr),
306 def LDSTUBri : F3_2<3, 0b001101, (outs IntRegs:$dst), (ins MEMri:$addr),
308 def LDSTUBArr : F3_1_asi<3, 0b011101, (outs IntRegs:$dst),
381 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
403 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
423 defm LDSB : LoadA<"ldsb", 0b001001, 0b011001, sextloadi8, IntRegs, i32>;
424 defm LDSH : LoadA<"ldsh", 0b001010, 0b011010, sextloadi16, IntRegs, i32>;
425 defm LDUB : LoadA<"ldub", 0b000001, 0b010001, zextloadi8, IntRegs, i32>;
426 defm LDUH : LoadA<"lduh", 0b000010, 0b010010, zextloadi16, IntRegs, i32>;
427 defm LD : LoadA<"ld", 0b000000, 0b010000, load, IntRegs, i32>;
466 defm STB : StoreA<"stb", 0b000101, 0b010101, truncstorei8, IntRegs, i32>;
467 defm STH : StoreA<"sth", 0b000110, 0b010110, truncstorei16, IntRegs, i32>;
468 defm ST : StoreA<"st", 0b000100, 0b010100, store, IntRegs, i32>;
509 (outs IntRegs:$dst), (ins MEMrr:$addr, IntRegs:$val),
513 (outs IntRegs:$dst), (ins MEMri:$addr, IntRegs:$val),
517 (outs IntRegs:$dst), (ins MEMrr:$addr, i8imm:$asi, IntRegs:$val),
525 (outs IntRegs:$rd), (ins i32imm:$imm22),
535 defm AND : F3_12<"and", 0b000001, and, IntRegs, i32, simm13Op>;
538 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
542 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
545 defm OR : F3_12<"or", 0b000010, or, IntRegs, i32, simm13Op>;
548 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
552 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
554 defm XOR : F3_12<"xor", 0b000011, xor, IntRegs, i32, simm13Op>;
557 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
561 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
574 defm SLL : F3_12<"sll", 0b100101, shl, IntRegs, i32, simm13Op>;
575 defm SRL : F3_12<"srl", 0b100110, srl, IntRegs, i32, simm13Op>;
576 defm SRA : F3_12<"sra", 0b100111, sra, IntRegs, i32, simm13Op>;
579 defm ADD : F3_12<"add", 0b000000, add, IntRegs, i32, simm13Op>;
584 (outs IntRegs:$dst), (ins MEMri:$addr),
589 defm ADDCC : F3_12<"addcc", 0b010000, addc, IntRegs, i32, simm13Op>;
595 defm ADDE : F3_12<"addxcc", 0b011000, adde, IntRegs, i32, simm13Op>;
598 defm SUB : F3_12 <"sub" , 0b000100, sub, IntRegs, i32, simm13Op>;
600 defm SUBE : F3_12 <"subxcc" , 0b011100, sube, IntRegs, i32, simm13Op>;
603 defm SUBCC : F3_12 <"subcc", 0b010100, subc, IntRegs, i32, simm13Op>;
611 (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
615 (outs), (ins IntRegs:$rs1, simm13Op:$simm13),
623 defm SMUL : F3_12 <"smul", 0b001011, mul, IntRegs, i32, simm13Op>;
788 def JMPLrr: F3_1<2, 0b111000, (outs IntRegs:$dst), (ins MEMrr:$addr),
790 def JMPLri: F3_2<2, 0b111000, (outs IntRegs:$dst), (ins MEMri:$addr),
819 def rr : TRAPSPrr<0b111010, (outs), (ins IntRegs:$rs1, IntRegs:$rs2,
822 def ri : TRAPSPri<0b111010, (outs), (ins IntRegs:$rs1, i32imm:$imm,
836 (outs IntRegs:$rd), (ins ASRRegs:$rs1),
843 (outs IntRegs:$rd), (ins),
848 (outs IntRegs:$rd), (ins),
853 (outs IntRegs:$rd), (ins),
859 (outs ASRRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
862 (outs ASRRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
869 (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
872 (outs), (ins IntRegs:$rs1, simm13Op:$simm13),
878 (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
881 (outs), (ins IntRegs:$rs1, simm13Op:$simm13),
887 (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
890 (outs), (ins IntRegs:$rs1, simm13Op:$simm13),
1111 (outs IntRegs:$rd),
1112 (ins IntRegs:$rs1, IntRegs:$rs2, TLSSym:$sym),
1119 (outs IntRegs:$dst), (ins MEMrr:$addr, TLSSym:$sym),
1144 : F4_1<0b101100, (outs IntRegs:$rd),
1145 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
1150 : F4_2<0b101100, (outs IntRegs:$rd),
1151 (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond),
1159 : F4_1<0b101100, (outs IntRegs:$rd),
1160 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
1164 : F4_2<0b101100, (outs IntRegs:$rd),
1165 (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond),
1269 : F4_1<0b101100, (outs IntRegs:$rd),
1270 (ins FCCRegs:$cc, IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
1273 : F4_2<0b101100, (outs IntRegs:$rd),
1274 (ins FCCRegs:$cc, i32imm:$simm11, IntRegs:$f, CCOp:$cond),
1297 (outs IntRegs:$rd), (ins IntRegs:$rs2),
1314 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
1315 IntRegs:$swap),
1335 (outs IntRegs:$rd), (ins PRRegs:$rs1),
1342 (outs PRRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
1345 (outs PRRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
1429 def : Pat<(build_vector (i32 IntRegs:$a1), (i32 IntRegs:$a2)),
1431 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)), (i32 IntRegs:$a1), sub_even),
1432 (i32 IntRegs:$a2), sub_odd)>;