Lines Matching refs:Num
88 unsigned Num; member
146 createReg(RegisterKind Kind, unsigned Num, SMLoc StartLoc, SMLoc EndLoc) { in createReg() argument
149 Op->Reg.Num = Num; in createReg()
153 createAccessReg(unsigned Num, SMLoc StartLoc, SMLoc EndLoc) { in createAccessReg() argument
155 Op->AccessReg = Num; in createAccessReg()
204 return Reg.Num; in getReg()
361 unsigned Num; member
514 if (Name.substr(1).getAsInteger(10, Reg.Num)) in parseRegister()
518 if (Prefix == 'r' && Reg.Num < 16) in parseRegister()
520 else if (Prefix == 'f' && Reg.Num < 16) in parseRegister()
522 else if (Prefix == 'v' && Reg.Num < 32) in parseRegister()
524 else if (Prefix == 'a' && Reg.Num < 16) in parseRegister()
546 if (Regs && Regs[Reg.Num] == 0) in parseRegister()
548 if (Reg.Num == 0 && IsAddress) in parseRegister()
551 Reg.Num = Regs[Reg.Num]; in parseRegister()
567 Operands.push_back(SystemZOperand::createReg(Kind, Reg.Num, in parseRegister()
599 Index = SystemZMC::VR128Regs[Reg.Num]; in parseAddress()
601 if (Reg.Num == 0) in parseAddress()
606 Index = Regs[Reg.Num]; in parseAddress()
608 Base = Regs[Reg.Num]; in parseAddress()
623 Base = Reg.Num; in parseAddress()
690 RegNo = SystemZMC::GR64Regs[Reg.Num]; in ParseRegister()
692 RegNo = SystemZMC::FP64Regs[Reg.Num]; in ParseRegister()
694 RegNo = SystemZMC::VR128Regs[Reg.Num]; in ParseRegister()
843 Operands.push_back(SystemZOperand::createAccessReg(Reg.Num, in parseAccessReg()