Lines Matching refs:V1
497 bits<5> V1;
502 let Inst{39-36} = V1{3-0};
506 let Inst{11} = V1{4};
516 bits<5> V1;
522 let Inst{39-36} = V1{3-0};
527 let Inst{11} = V1{4};
537 bits<5> V1;
543 let Inst{39-36} = V1{3-0};
547 let Inst{11} = V1{4};
558 bits<5> V1;
565 let Inst{39-36} = V1{3-0};
571 let Inst{11} = V1{4};
583 bits<5> V1;
590 let Inst{39-36} = V1{3-0};
595 let Inst{11} = V1{4};
609 bits<5> V1;
616 let Inst{39-36} = V1{3-0};
625 let Inst{11} = V1{4};
639 bits<5> V1;
646 let Inst{39-36} = V1{3-0};
656 let Inst{11} = V1{4};
668 bits<5> V1;
676 let Inst{39-36} = V1{3-0};
683 let Inst{11} = V1{4};
698 bits<5> V1;
706 let Inst{39-36} = V1{3-0};
716 let Inst{11} = V1{4};
728 bits<5> V1;
736 let Inst{39-36} = V1{3-0};
743 let Inst{11} = V1{4};
755 bits<5> V1;
760 let Inst{39-36} = V1{3-0};
764 let Inst{11} = V1{4};
774 bits<5> V1;
780 let Inst{39-36} = V1{3-0};
784 let Inst{11} = V1{4};
795 bits<5> V1;
801 let Inst{39-36} = V1{3-0};
805 let Inst{11} = V1{4};
836 bits<5> V1;
841 let Inst{39-36} = V1{3-0};
844 let Inst{11} = V1{4};
855 bits<5> V1;
860 let Inst{39-36} = V1{3-0};
863 let Inst{11} = V1{4};
963 : InstVRIa<opcode, (outs VR128:$V1), (ins), mnemonic#"\t$V1", []> {
984 : InstVRSa<opcode, (outs VR128:$V1, VR128:$V3), (ins bdaddr12only:$BD2),
985 mnemonic#"\t$V1, $V3, $BD2", []> {
1040 : InstVRX<opcode, (outs), (ins tr.op:$V1, bdxaddr12only:$XBD2),
1041 mnemonic#"\t$V1, $XBD2",
1042 [(set tr.op:$V1, (tr.vt (operator bdxaddr12only:$XBD2)))]> {
1050 : InstVRSb<opcode, (outs), (ins VR128:$V1, GR32:$R3, bdaddr12only:$BD2),
1051 mnemonic#"\t$V1, $R3, $BD2",
1052 [(operator VR128:$V1, GR32:$R3, bdaddr12only:$BD2)]> {
1065 : InstVRSa<opcode, (outs), (ins VR128:$V1, VR128:$V3, bdaddr12only:$BD2),
1066 mnemonic#"\t$V1, $V3, $BD2", []> {
1332 : InstVRIa<opcode, (outs tr.op:$V1), (ins imm:$I2),
1333 mnemonic#"\t$V1, $I2",
1334 [(set tr.op:$V1, (tr.vt (operator imm:$I2)))]> {
1341 : InstVRRa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2),
1342 mnemonic#"\t$V1, $V2",
1343 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2))))]> {
1362 : InstVRX<opcode, (outs tr.op:$V1), (ins bdxaddr12only:$XBD2),
1363 mnemonic#"\t$V1, $XBD2",
1364 [(set tr.op:$V1, (tr.vt (operator bdxaddr12only:$XBD2)))]> {
1584 : InstVRIb<opcode, (outs tr.op:$V1), (ins imm32zx8:$I2, imm32zx8:$I3),
1585 mnemonic#"\t$V1, $I2, $I3",
1586 [(set tr.op:$V1, (tr.vt (operator imm32zx8:$I2, imm32zx8:$I3)))]> {
1592 : InstVRIc<opcode, (outs tr1.op:$V1), (ins tr2.op:$V3, imm32zx16:$I2),
1593 mnemonic#"\t$V1, $V3, $I2",
1594 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V3),
1601 : InstVRIe<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, imm32zx12:$I3),
1602 mnemonic#"\t$V1, $V2, $I3",
1603 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
1610 : InstVRRa<opcode, (outs VR128:$V1), (ins VR128:$V2, imm32zx4:$M3),
1611 mnemonic#"\t$V1, $V2, $M3", []> {
1619 : InstVRRb<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, tr2.op:$V3),
1620 mnemonic#"\t$V1, $V2, $V3",
1621 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
1643 : InstVRRc<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, tr2.op:$V3),
1644 mnemonic#"\t$V1, $V2, $V3",
1645 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
1665 : InstVRRf<opcode, (outs tr.op:$V1), (ins GR64:$R2, GR64:$R3),
1666 mnemonic#"\t$V1, $R2, $R3",
1667 [(set tr.op:$V1, (tr.vt (operator GR64:$R2, GR64:$R3)))]>;
1671 : InstVRSa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V3, shift12only:$BD2),
1672 mnemonic#"\t$V1, $V3, $BD2",
1673 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V3),
1680 : InstVRSb<opcode, (outs VR128:$V1), (ins GR32:$R3, bdaddr12only:$BD2),
1681 mnemonic#"\t$V1, $R3, $BD2",
1682 [(set VR128:$V1, (operator GR32:$R3, bdaddr12only:$BD2))]> {
1698 : InstVRX<opcode, (outs VR128:$V1), (ins bdxaddr12only:$XBD2, imm32zx4:$M3),
1699 mnemonic#"\t$V1, $XBD2, $M3",
1700 [(set tr.op:$V1, (tr.vt (operator bdxaddr12only:$XBD2,
1708 : InstVRV<opcode, (outs), (ins VR128:$V1, bdvaddr12only:$VBD2, index:$M3),
1709 mnemonic#"\t$V1, $VBD2, $M3", []> {
1717 : InstVRX<opcode, (outs), (ins tr.op:$V1, bdxaddr12only:$XBD2, index:$M3),
1718 mnemonic#"\t$V1, $XBD2, $M3",
1719 [(operator (tr.vt tr.op:$V1), bdxaddr12only:$XBD2, index:$M3)]> {
1868 : InstVRRa<opcode, (outs), (ins tr.op:$V1, tr.op:$V2),
1869 mnemonic#"\t$V1, $V2",
1870 [(operator (tr.vt tr.op:$V1), (tr.vt tr.op:$V2))]> {
1905 : InstVRIa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V1src, imm:$I2, index:$M3),
1906 mnemonic#"\t$V1, $I2, $M3",
1907 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src),
1909 let Constraints = "$V1 = $V1src";
1915 : InstVRId<opcode, (outs tr1.op:$V1),
1917 mnemonic#"\t$V1, $V2, $V3, $I4",
1918 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
1926 : InstVRRa<opcode, (outs tr1.op:$V1),
1928 mnemonic#"\t$V1, $V2, $M4, $M5",
1929 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
1939 : InstVRRb<opcode, (outs tr1.op:$V1),
1941 mnemonic#"\t$V1, $V2, $V3, $M5",
1942 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
1955 def : InstAlias<mnemonic#"\t$V1, $V2, $V3",
1956 (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2,
1961 def : InstAlias<mnemonic#"s\t$V1, $V2, $V3",
1962 (!cast<Instruction>(NAME#"S") tr1.op:$V1, tr2.op:$V2,
1968 : InstVRRc<opcode, (outs tr1.op:$V1),
1970 mnemonic#"\t$V1, $V2, $V3, $M4",
1971 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
1980 : InstVRRd<opcode, (outs tr1.op:$V1),
1982 mnemonic#"\t$V1, $V2, $V3, $V4",
1983 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
1992 : InstVRRe<opcode, (outs tr1.op:$V1),
1994 mnemonic#"\t$V1, $V2, $V3, $V4",
1995 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
2004 : InstVRSb<opcode, (outs tr1.op:$V1),
2006 mnemonic#"\t$V1, $R3, $BD2",
2007 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src),
2010 let Constraints = "$V1 = $V1src";
2017 : InstVRV<opcode, (outs VR128:$V1),
2019 mnemonic#"\t$V1, $VBD2, $M3", []> {
2020 let Constraints = "$V1 = $V1src";
2028 : InstVRX<opcode, (outs tr1.op:$V1),
2030 mnemonic#"\t$V1, $XBD2, $M3",
2031 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src),
2034 let Constraints = "$V1 = $V1src";
2042 : InstVRId<opcode, (outs tr1.op:$V1),
2044 mnemonic#"\t$V1, $V2, $V3, $I4",
2045 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src),
2049 let Constraints = "$V1 = $V1src";
2057 : InstVRRd<opcode, (outs tr1.op:$V1),
2059 mnemonic#"\t$V1, $V2, $V3, $V4, $M6",
2060 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
2074 def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $V4",
2075 (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2,
2080 def : InstAlias<mnemonic#"s\t$V1, $V2, $V3, $V4",
2081 (!cast<Instruction>(NAME#"S") tr1.op:$V1, tr2.op:$V2,
2410 : Alias<6, (outs tr1.op:$V1), (ins tr2.op:$V2),
2411 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2))))]>;
2416 : Alias<6, (outs tr.op:$V1), (ins mode:$XBD2),
2417 [(set tr.op:$V1, (tr.vt (operator mode:$XBD2)))]>;
2422 : Alias<6, (outs), (ins tr.op:$V1, mode:$XBD2),
2423 [(operator (tr.vt tr.op:$V1), mode:$XBD2)]>;
2443 : Alias<6, (outs VR128:$V1), (ins cls:$R2, cls:$R3), []>;