266     unsigned BaseReg, IndexReg, TmpReg, Scale;  member in __anon720aab8e0111::X86AsmParser::IntelExprStateMachine
276       State(IES_PLUS), PrevState(IES_ERROR), BaseReg(0), IndexReg(0), TmpReg(0),  in IntelExprStateMachine()
280     unsigned getBaseReg() { return BaseReg; }  in getBaseReg()
386           if (!BaseReg) {  in onPlus()
387             BaseReg = TmpReg;  in onPlus()
423           if (!BaseReg) {  in onMinus()
424             BaseReg = TmpReg;  in onMinus()
602           if (!BaseReg) {  in onRBrac()
603             BaseReg = TmpReg;  in onRBrac()
713   CreateMemForInlineAsm(unsigned SegReg, const MCExpr *Disp, unsigned BaseReg,
833 static bool CheckBaseRegAndIndexReg(unsigned BaseReg, unsigned IndexReg,  in CheckBaseRegAndIndexReg()  argument
838   if (BaseReg != 0 && IndexReg != 0) {  in CheckBaseRegAndIndexReg()
839     if (X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg) &&  in CheckBaseRegAndIndexReg()
846     if (X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg) &&  in CheckBaseRegAndIndexReg()
853     if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg)) {  in CheckBaseRegAndIndexReg()
859       if (((BaseReg == X86::BX || BaseReg == X86::BP) &&  in CheckBaseRegAndIndexReg()
861           ((BaseReg == X86::SI || BaseReg == X86::DI) &&  in CheckBaseRegAndIndexReg()
879   unsigned diReg = Op1.Mem.BaseReg;  in doSrcDstMatch()
880   unsigned siReg = Op2.Mem.BaseReg;  in doSrcDstMatch()
1068     unsigned SegReg, const MCExpr *Disp, unsigned BaseReg, unsigned IndexReg,  in CreateMemForInlineAsm()  argument
1105   BaseReg = BaseReg ? BaseReg : 1;  in CreateMemForInlineAsm()
1106   return X86Operand::CreateMem(getPointerWidth(), SegReg, Disp, BaseReg,  in CreateMemForInlineAsm()
1340   int BaseReg = SM.getBaseReg();  in ParseIntelBracExpression()  local
1345     if (!BaseReg && !IndexReg) {  in ParseIntelBracExpression()
1352     if (CheckBaseRegAndIndexReg(BaseReg, IndexReg, ErrMsg)) {  in ParseIntelBracExpression()
1356     return X86Operand::CreateMem(getPointerWidth(), SegReg, Disp, BaseReg,  in ParseIntelBracExpression()
1361   return CreateMemForInlineAsm(SegReg, Disp, BaseReg, IndexReg, Scale, Start,  in ParseIntelBracExpression()
1955   unsigned BaseReg = 0, IndexReg = 0, Scale = 1;  in ParseMemOperand()  local
1961     if (ParseRegister(BaseReg, StartLoc, EndLoc)) return nullptr;  in ParseMemOperand()
1962     if (BaseReg == X86::EIZ || BaseReg == X86::RIZ) {  in ParseMemOperand()
2003           if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg) &&  in ParseMemOperand()
2042   if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg) &&  in ParseMemOperand()
2043       (is64BitMode() || (BaseReg != X86::BX && BaseReg != X86::BP &&  in ParseMemOperand()
2044                          BaseReg != X86::SI && BaseReg != X86::DI)) &&  in ParseMemOperand()
2045       BaseReg != X86::DX) {  in ParseMemOperand()
2049   if (BaseReg == 0 &&  in ParseMemOperand()
2056   if (CheckBaseRegAndIndexReg(BaseReg, IndexReg, ErrMsg)) {  in ParseMemOperand()
2061   if (SegReg || BaseReg || IndexReg)  in ParseMemOperand()
2062     return X86Operand::CreateMem(getPointerWidth(), SegReg, Disp, BaseReg,  in ParseMemOperand()
2256         Op.Mem.BaseReg == MatchRegisterName("dx") && Op.Mem.IndexReg == 0) {  in ParseInstruction()
2258       Operands.back() = X86Operand::CreateReg(Op.Mem.BaseReg, Loc, Loc);  in ParseInstruction()
2268         Op.Mem.BaseReg == MatchRegisterName("dx") && Op.Mem.IndexReg == 0) {  in ParseInstruction()
2270       Operands[1] = X86Operand::CreateReg(Op.Mem.BaseReg, Loc, Loc);  in ParseInstruction()