175 static void translateRegister(MCInst &mcInst, Reg reg) {  in translateRegister()  argument
184   mcInst.addOperand(MCOperand::createReg(llvmRegnum));  in translateRegister()
241 static bool translateSrcIndex(MCInst &mcInst, InternalInstruction &insn) {  in translateSrcIndex()  argument
253   mcInst.addOperand(baseReg);  in translateSrcIndex()
257   mcInst.addOperand(segmentReg);  in translateSrcIndex()
266 static bool translateDstIndex(MCInst &mcInst, InternalInstruction &insn) {  in translateDstIndex()  argument
278   mcInst.addOperand(baseReg);  in translateDstIndex()
288 static void translateImmediate(MCInst &mcInst, uint64_t immediate,  in translateImmediate()  argument
346       switch (mcInst.getOpcode()) {  in translateImmediate()
374       mcInst.setOpcode(NewOpc);  in translateImmediate()
380       switch (mcInst.getOpcode()) {  in translateImmediate()
406       mcInst.setOpcode(NewOpc);  in translateImmediate()
411       switch (mcInst.getOpcode()) {  in translateImmediate()
535       mcInst.setOpcode(NewOpc);  in translateImmediate()
543     mcInst.addOperand(MCOperand::createReg(X86::XMM0 + (immediate >> 4)));  in translateImmediate()
546     mcInst.addOperand(MCOperand::createReg(X86::YMM0 + (immediate >> 4)));  in translateImmediate()
549     mcInst.addOperand(MCOperand::createReg(X86::ZMM0 + (immediate >> 4)));  in translateImmediate()
552     mcInst.addOperand(MCOperand::createReg(X86::BND0 + (immediate >> 4)));  in translateImmediate()
579                                mcInst, Dis))  in translateImmediate()
580     mcInst.addOperand(MCOperand::createImm(immediate));  in translateImmediate()
586     mcInst.addOperand(segmentReg);  in translateImmediate()
596 static bool translateRMRegister(MCInst &mcInst,  in translateRMRegister()  argument
618     mcInst.addOperand(MCOperand::createReg(X86::x)); break;  in translateRMRegister()
634 static bool translateRMMemory(MCInst &mcInst, InternalInstruction &insn,  in translateRMMemory()  argument
677     uint32_t Opcode = mcInst.getOpcode();  in translateRMMemory()
798   mcInst.addOperand(baseReg);  in translateRMMemory()
799   mcInst.addOperand(scaleAmount);  in translateRMMemory()
800   mcInst.addOperand(indexReg);  in translateRMMemory()
803                                insn.displacementSize, mcInst, Dis))  in translateRMMemory()
804     mcInst.addOperand(displacement);  in translateRMMemory()
805   mcInst.addOperand(segmentReg);  in translateRMMemory()
817 static bool translateRM(MCInst &mcInst, const OperandSpecifier &operand,  in translateRM()  argument
845     return translateRMRegister(mcInst, insn);  in translateRM()
862     return translateRMMemory(mcInst, insn, Dis);  in translateRM()
871 static void translateFPRegister(MCInst &mcInst,  in translateFPRegister()  argument
873   mcInst.addOperand(MCOperand::createReg(X86::ST0 + stackPos));  in translateFPRegister()
882 static bool translateMaskRegister(MCInst &mcInst,  in translateMaskRegister()  argument
889   mcInst.addOperand(MCOperand::createReg(X86::K0 + maskRegNum));  in translateMaskRegister()
900 static bool translateOperand(MCInst &mcInst, const OperandSpecifier &operand,  in translateOperand()  argument
908     translateRegister(mcInst, insn.reg);  in translateOperand()
911     return translateMaskRegister(mcInst, insn.writemask);  in translateOperand()
913     return translateRM(mcInst, operand, insn, Dis);  in translateOperand()
928     translateImmediate(mcInst,  in translateOperand()
935     return translateSrcIndex(mcInst, insn);  in translateOperand()
937     return translateDstIndex(mcInst, insn);  in translateOperand()
943     translateRegister(mcInst, insn.opcodeRegister);  in translateOperand()
946     translateFPRegister(mcInst, insn.modRM & 7);  in translateOperand()
949     translateRegister(mcInst, insn.vvvv);  in translateOperand()
952     return translateOperand(mcInst, insn.operands[operand.type - TYPE_DUP0],  in translateOperand()
963 static bool translateInstruction(MCInst &mcInst,  in translateInstruction()  argument
971   mcInst.clear();  in translateInstruction()
972   mcInst.setOpcode(insn.instructionID);  in translateInstruction()
977     if(mcInst.getOpcode() == X86::REP_PREFIX)  in translateInstruction()
978       mcInst.setOpcode(X86::XRELEASE_PREFIX);  in translateInstruction()
979     else if(mcInst.getOpcode() == X86::REPNE_PREFIX)  in translateInstruction()
980       mcInst.setOpcode(X86::XACQUIRE_PREFIX);  in translateInstruction()
987       if (translateOperand(mcInst, Op, insn, Dis)) {  in translateInstruction()