Lines Matching refs:into

23 match them.   For example, this should turn into a horizontal add:
50 into:
103 into:
213 This compiles into:
258 "fold" it into the uses, producing something like this:
326 Apply the same transformation that merged four float into a single 128-bit load
332 specified. We should turn int_x86_sse_max_ss and X86ISD::FMIN etc. into other
377 "y" looks good, but "x" does silly movzwl stuff around into a GPR.  It seems
401 CodeGen/X86/vec_align.ll tests whether we can turn 4 scalar loads into a single
407 2. The code for turning 4 x load into a single vector load is target 
409 3. The code for turning 4 x load into a vector load can only handle a direct 
418 We should lower store(fneg(load p), q) into an integer load+xor+store, which
447 Note the load into xmm0, then xor (to negate), then store.  In PIC mode,
452 until post-legalize, and at that point, the fneg has been custom expanded into 
458 Non-SSE4 insert into 16 x i8 is atrociously bad.
564 We compile vector multiply-by-constant into poor code:
571 On targets without SSE4.1, this compiles into:
618 into:
654 We should transform a shuffle of two vectors of constants into a single vector
655 of constants. Also, insertelement of a constant into a vector of constants
730 In fpstack mode, this compiles into:
743 in SSE mode, it compiles into significantly slower code:
760 These should compile into the same code (PR6214): Perhaps instcombine should
761 canonicalize the former into the later?
839 turn into hsubpd also.
848 Should compile into cvttpd2dq instead of being scalarized into 2 cvttsd2si.