Lines Matching refs:DCI
14056 DAGCombinerInfo &DCI, in getRsqrtEstimate() argument
14077 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals; in getRsqrtEstimate()
14083 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op); in getRsqrtEstimate()
14089 DAGCombinerInfo &DCI, in getRecipEstimate() argument
14109 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals; in getRecipEstimate()
14114 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op); in getRecipEstimate()
22647 TargetLowering::DAGCombinerInfo &DCI, in PerformShuffleCombine256() argument
22716 return DCI.CombineTo(N, InsV); in PerformShuffleCombine256()
22727 return DCI.CombineTo(N, InsV); in PerformShuffleCombine256()
22734 return DCI.CombineTo(N, InsV); in PerformShuffleCombine256()
22751 TargetLowering::DAGCombinerInfo &DCI, in combineX86ShuffleChain() argument
22777 DCI.CombineTo(Root.getNode(), getZeroVector(RootVT, Subtarget, DAG, DL)); in combineX86ShuffleChain()
22779 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Input), in combineX86ShuffleChain()
22816 DCI.AddToWorklist(Op.getNode()); in combineX86ShuffleChain()
22821 DCI.AddToWorklist(Op.getNode()); in combineX86ShuffleChain()
22822 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op), in combineX86ShuffleChain()
22834 DCI.AddToWorklist(Op.getNode()); in combineX86ShuffleChain()
22836 DCI.AddToWorklist(Op.getNode()); in combineX86ShuffleChain()
22837 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op), in combineX86ShuffleChain()
22848 DCI.AddToWorklist(Op.getNode()); in combineX86ShuffleChain()
22850 DCI.AddToWorklist(Op.getNode()); in combineX86ShuffleChain()
22851 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op), in combineX86ShuffleChain()
22882 DCI.AddToWorklist(Op.getNode()); in combineX86ShuffleChain()
22884 DCI.AddToWorklist(Op.getNode()); in combineX86ShuffleChain()
22885 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op), in combineX86ShuffleChain()
22915 DCI.AddToWorklist(Op.getNode()); in combineX86ShuffleChain()
22918 DCI.AddToWorklist(PSHUFBMaskOp.getNode()); in combineX86ShuffleChain()
22920 DCI.AddToWorklist(Op.getNode()); in combineX86ShuffleChain()
22921 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op), in combineX86ShuffleChain()
22963 TargetLowering::DAGCombinerInfo &DCI, in combineX86ShufflesRecursively() argument
23044 HasPSHUFB, DAG, DCI, Subtarget)) in combineX86ShufflesRecursively()
23056 HasPSHUFB, DAG, DCI, Subtarget)) in combineX86ShufflesRecursively()
23072 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI, in combineX86ShufflesRecursively()
23125 TargetLowering::DAGCombinerInfo &DCI) { in combineRedundantDWordShuffle() argument
23259 TargetLowering::DAGCombinerInfo &DCI) { in combineRedundantHalfShuffle() argument
23296 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true); in combineRedundantHalfShuffle()
23314 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true); in combineRedundantHalfShuffle()
23321 TargetLowering::DAGCombinerInfo &DCI, in PerformTargetShuffleCombine() argument
23375 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true); in PerformTargetShuffleCombine()
23386 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI)) in PerformTargetShuffleCombine()
23399 DCI.AddToWorklist(V.getNode()); in PerformTargetShuffleCombine()
23402 DCI.AddToWorklist(V.getNode()); in PerformTargetShuffleCombine()
23435 DCI.AddToWorklist(V.getNode()); in PerformTargetShuffleCombine()
23446 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI)) in PerformTargetShuffleCombine()
23517 TargetLowering::DAGCombinerInfo &DCI, in PerformShuffleCombine() argument
23526 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType())) in PerformShuffleCombine()
23538 return PerformShuffleCombine256(N, DAG, DCI, Subtarget); in PerformShuffleCombine()
23552 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() && in PerformShuffleCombine()
23603 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget); in PerformShuffleCombine()
23616 DCI, Subtarget)) in PerformShuffleCombine()
23628 TargetLowering::DAGCombinerInfo &DCI) { in XFormVExtractWithShuffleIntoLoad() argument
23629 if (DCI.isBeforeLegalizeOps()) in XFormVExtractWithShuffleIntoLoad()
23769 TargetLowering::DAGCombinerInfo &DCI) { in PerformEXTRACT_VECTOR_ELTCombine() argument
23770 if (SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI)) in PerformEXTRACT_VECTOR_ELTCombine()
23961 TargetLowering::DAGCombinerInfo &DCI, in PerformSELECTCombine() argument
24131 DCI.AddToWorklist(Cond.getNode()); in PerformSELECTCombine()
24385 !DCI.isBeforeLegalize() && !VT.is512BitVector()) { in PerformSELECTCombine()
24395 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() && in PerformSELECTCombine()
24396 !DCI.isBeforeLegalize() && in PerformSELECTCombine()
24432 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(), in PerformSELECTCombine()
24433 DCI.isBeforeLegalizeOps()); in PerformSELECTCombine()
24462 DCI.CommitTargetLoweringOpt(TLO); in PerformSELECTCombine()
24652 TargetLowering::DAGCombinerInfo &DCI, in PerformCMOVCombine() argument
24714 return DCI.CombineTo(N, Cond, SDValue()); in PerformCMOVCombine()
24731 return DCI.CombineTo(N, Cond, SDValue()); in PerformCMOVCombine()
24774 return DCI.CombineTo(N, Cond, SDValue()); in PerformCMOVCombine()
24795 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) { in PerformCMOVCombine()
24864 TargetLowering::DAGCombinerInfo &DCI) { in PerformMulCombine() argument
24869 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) in PerformMulCombine()
24944 DCI.CombineTo(N, NewMul, false); in PerformMulCombine()
25095 TargetLowering::DAGCombinerInfo &DCI, in PerformShiftCombine() argument
25117 TargetLowering::DAGCombinerInfo &DCI, in CMPEQCombine() argument
25251 TargetLowering::DAGCombinerInfo &DCI, in WidenMaskArithmetic() argument
25330 TargetLowering::DAGCombinerInfo &DCI, in VectorZextCombine() argument
25455 TargetLowering::DAGCombinerInfo &DCI, in PerformAndCombine() argument
25457 if (DCI.isBeforeLegalizeOps()) in PerformAndCombine()
25460 if (SDValue Zext = VectorZextCombine(N, DAG, DCI, Subtarget)) in PerformAndCombine()
25463 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget)) in PerformAndCombine()
25521 TargetLowering::DAGCombinerInfo &DCI, in PerformOrCombine() argument
25523 if (DCI.isBeforeLegalizeOps()) in PerformOrCombine()
25526 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget)) in PerformOrCombine()
25762 TargetLowering::DAGCombinerInfo &DCI, in PerformXorCombine() argument
25764 if (DCI.isBeforeLegalizeOps()) in PerformXorCombine()
25902 TargetLowering::DAGCombinerInfo &DCI, in PerformLOADCombine() argument
25916 if (RegVT.is256BitVector() && !DCI.isBeforeLegalizeOps() && in PerformLOADCombine()
25946 return DCI.CombineTo(N, NewVec, TF, true); in PerformLOADCombine()
25954 TargetLowering::DAGCombinerInfo &DCI, in PerformMLOADCombine() argument
26030 return DCI.CombineTo(N, NewVec, WideLd.getValue(1), true); in PerformMLOADCombine()
26891 TargetLowering::DAGCombinerInfo &DCI) { in PerformBTCombine() argument
26898 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in PerformBTCombine()
26899 !DCI.isBeforeLegalizeOps()); in PerformBTCombine()
26903 DCI.CommitTargetLoweringOpt(TLO); in PerformBTCombine()
27008 TargetLowering::DAGCombinerInfo &DCI, in PerformSExtCombine() argument
27030 if (!DCI.isBeforeLegalizeOps()) { in PerformSExtCombine()
27098 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget)) in PerformSExtCombine()
27147 TargetLowering::DAGCombinerInfo &DCI, in PerformZExtCombine() argument
27184 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget)) in PerformZExtCombine()
27325 TargetLowering::DAGCombinerInfo &DCI, in PerformSETCCCombine() argument
27366 TargetLowering::DAGCombinerInfo &DCI, in PerformBrCondCombine() argument
27501 X86TargetLowering::DAGCombinerInfo &DCI) { in PerformADCCombine() argument
27519 return DCI.CombineTo(N, Res1, CarryOut); in PerformADCCombine()
27617 TargetLowering::DAGCombinerInfo &DCI, in performVZEXTCombine() argument
27680 DAGCombinerInfo &DCI) const { in PerformDAGCombine()
27681 SelectionDAG &DAG = DCI.DAG; in PerformDAGCombine()
27685 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI); in PerformDAGCombine()
27689 return PerformSELECTCombine(N, DAG, DCI, Subtarget); in PerformDAGCombine()
27691 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget); in PerformDAGCombine()
27694 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI); in PerformDAGCombine()
27695 case ISD::MUL: return PerformMulCombine(N, DAG, DCI); in PerformDAGCombine()
27698 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget); in PerformDAGCombine()
27699 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget); in PerformDAGCombine()
27700 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget); in PerformDAGCombine()
27701 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget); in PerformDAGCombine()
27702 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget); in PerformDAGCombine()
27703 case ISD::MLOAD: return PerformMLOADCombine(N, DAG, DCI, Subtarget); in PerformDAGCombine()
27719 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI); in PerformDAGCombine()
27722 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget); in PerformDAGCombine()
27723 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget); in PerformDAGCombine()
27727 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget); in PerformDAGCombine()
27728 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget); in PerformDAGCombine()
27729 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget); in PerformDAGCombine()
27744 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget); in PerformDAGCombine()