Lines Matching refs:EXTLOAD
389 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand); in X86TargetLowering()
390 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand); in X86TargetLowering()
391 setLoadExtAction(ISD::EXTLOAD, MVT::f80, MVT::f16, Expand); in X86TargetLowering()
764 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand); in X86TargetLowering()
769 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand); in X86TargetLowering()
892 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Custom); in X86TargetLowering()
893 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Custom); in X86TargetLowering()
894 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Custom); in X86TargetLowering()
895 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Custom); in X86TargetLowering()
896 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Custom); in X86TargetLowering()
897 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8i8, Custom); in X86TargetLowering()
950 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2f32, Legal); in X86TargetLowering()
1116 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4f32, Legal); in X86TargetLowering()
1319 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8f32, Legal); in X86TargetLowering()
12962 ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(), FudgePtr, in LowerUINT_TO_FP()
15270 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD) in LowerExtendedLoad()