4584   MVT OpVT = Op.getSimpleValueType();  in Insert1BitVector()  local
4586   unsigned NumElems = OpVT.getVectorNumElements();  in Insert1BitVector()
4601   SDValue Undef = DAG.getUNDEF(OpVT);  in Insert1BitVector()
4603     DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef, SubVec, ZeroIdx);  in Insert1BitVector()
4605     return DAG.getNode(X86ISD::VSHLI, dl, OpVT, WideSubVec,  in Insert1BitVector()
4611     WideSubVec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, WideSubVec,  in Insert1BitVector()
4613     return ShiftRight ? DAG.getNode(X86ISD::VSRLI, dl, OpVT, WideSubVec,  in Insert1BitVector()
4620     Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);  in Insert1BitVector()
4621     Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);  in Insert1BitVector()
4623     return DAG.getNode(ISD::OR, dl, OpVT, Vec, WideSubVec);  in Insert1BitVector()
4629     WideSubVec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec,  in Insert1BitVector()
4632     Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);  in Insert1BitVector()
4633     Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);  in Insert1BitVector()
4634     return DAG.getNode(ISD::OR, dl, OpVT, Vec, WideSubVec);  in Insert1BitVector()
4641   return DAG.getVectorShuffle(OpVT, dl, WideSubVec, Vec, Mask);  in Insert1BitVector()
11846   MVT OpVT = Op.getSimpleValueType();  in LowerSCALAR_TO_VECTOR()  local
11850   if (!OpVT.is128BitVector()) {  in LowerSCALAR_TO_VECTOR()
11852     unsigned SizeFactor = OpVT.getSizeInBits()/128;  in LowerSCALAR_TO_VECTOR()
11853     MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),  in LowerSCALAR_TO_VECTOR()
11854                                  OpVT.getVectorNumElements() / SizeFactor);  in LowerSCALAR_TO_VECTOR()
11859     return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);  in LowerSCALAR_TO_VECTOR()
11862   if (OpVT == MVT::v1i64 &&  in LowerSCALAR_TO_VECTOR()
11867   assert(OpVT.is128BitVector() && "Expected an SSE type!");  in LowerSCALAR_TO_VECTOR()
11869       OpVT, DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, AnyExt));  in LowerSCALAR_TO_VECTOR()
11915   MVT OpVT = Op.getSimpleValueType();  in LowerINSERT_SUBVECTOR()  local
11922   if ((IdxVal == OpVT.getVectorNumElements() / 2) &&  in LowerINSERT_SUBVECTOR()
11924       OpVT.is256BitVector() && SubVecVT.is128BitVector()) {  in LowerINSERT_SUBVECTOR()
11938                                     OpVT, AS, Alignment, &Fast) && Fast) {  in LowerINSERT_SUBVECTOR()
11940           if (SDValue Ld = EltsFromConsecutiveLoads(OpVT, Ops, dl, DAG, false))  in LowerINSERT_SUBVECTOR()
11947   if ((OpVT.is256BitVector() || OpVT.is512BitVector()) &&  in LowerINSERT_SUBVECTOR()
11951   if (OpVT.is512BitVector() && SubVecVT.is256BitVector())  in LowerINSERT_SUBVECTOR()
11954   if (OpVT.getVectorElementType() == MVT::i1)  in LowerINSERT_SUBVECTOR()
14462   MVT OpVT = Op1.getSimpleValueType();  in LowerVSETCC()  local
14463   if (OpVT.getVectorElementType() == MVT::i1)  in LowerVSETCC()
14470         (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))  in LowerVSETCC()
14478         (OpVT.getVectorElementType().getSizeInBits() < 32 &&  in LowerVSETCC()
14479          OpVT.getVectorElementType().getSizeInBits() >= 8))  in LowerVSETCC()
14481                          DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));  in LowerVSETCC()
17810   MVT OpVT = VT;  in LowerCTLZ()  local
17820     OpVT = MVT::i32;  in LowerCTLZ()
17821     Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);  in LowerCTLZ()
17825   SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);  in LowerCTLZ()
17831     DAG.getConstant(NumBits + NumBits - 1, dl, OpVT),  in LowerCTLZ()
17835   Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);  in LowerCTLZ()
17838   Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,  in LowerCTLZ()
17839                    DAG.getConstant(NumBits - 1, dl, OpVT));  in LowerCTLZ()
17849   EVT OpVT = VT;  in LowerCTLZ_ZERO_UNDEF()  local
17859     OpVT = MVT::i32;  in LowerCTLZ_ZERO_UNDEF()
17860     Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);  in LowerCTLZ_ZERO_UNDEF()
17864   SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);  in LowerCTLZ_ZERO_UNDEF()
17868   Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,  in LowerCTLZ_ZERO_UNDEF()
17869                    DAG.getConstant(NumBits - 1, dl, OpVT));  in LowerCTLZ_ZERO_UNDEF()
24125     EVT OpVT = LHS.getValueType();  in PerformSELECTCombine()  local
24126     if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&  in PerformSELECTCombine()
24127         (OpVT.getVectorElementType() == MVT::i8 ||  in PerformSELECTCombine()
24128          OpVT.getVectorElementType() == MVT::i16) &&  in PerformSELECTCombine()
24130       Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);  in PerformSELECTCombine()
24132       return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);  in PerformSELECTCombine()
26912   EVT VT = N->getValueType(0), OpVT = Op.getValueType();  in PerformVZEXT_MOVLCombine()  local
26915       OpVT.getVectorElementType().getSizeInBits()) {  in PerformVZEXT_MOVLCombine()
27622   MVT OpVT = Op.getSimpleValueType();  in performVZEXTCombine()  local
27623   MVT OpEltVT = OpVT.getVectorElementType();  in performVZEXTCombine()
27638       assert(OpVT == InnerVT && "Types must match for vzext!");  in performVZEXTCombine()
27650     return DAG.getNode(X86ISD::VZEXT, DL, VT, DAG.getBitcast(OpVT, V));  in performVZEXTCombine()
27664         if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {  in performVZEXTCombine()
27665           int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();  in performVZEXTCombine()
27671         Op = DAG.getBitcast(OpVT, OrigV);  in performVZEXTCombine()