Lines Matching refs:RegVT

2700       EVT RegVT = VA.getLocVT();  in LowerFormalArguments()  local
2702 if (RegVT == MVT::i32) in LowerFormalArguments()
2704 else if (Is64Bit && RegVT == MVT::i64) in LowerFormalArguments()
2706 else if (RegVT == MVT::f32) in LowerFormalArguments()
2708 else if (RegVT == MVT::f64) in LowerFormalArguments()
2710 else if (RegVT == MVT::f128) in LowerFormalArguments()
2712 else if (RegVT.is512BitVector()) in LowerFormalArguments()
2714 else if (RegVT.is256BitVector()) in LowerFormalArguments()
2716 else if (RegVT.is128BitVector()) in LowerFormalArguments()
2718 else if (RegVT == MVT::x86mmx) in LowerFormalArguments()
2720 else if (RegVT == MVT::i1) in LowerFormalArguments()
2722 else if (RegVT == MVT::v8i1) in LowerFormalArguments()
2724 else if (RegVT == MVT::v16i1) in LowerFormalArguments()
2726 else if (RegVT == MVT::v32i1) in LowerFormalArguments()
2728 else if (RegVT == MVT::v64i1) in LowerFormalArguments()
2734 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); in LowerFormalArguments()
2740 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, in LowerFormalArguments()
2743 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, in LowerFormalArguments()
2750 if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1) in LowerFormalArguments()
3187 EVT RegVT = VA.getLocVT(); in LowerCall() local
3196 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg); in LowerCall()
3199 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg); in LowerCall()
3204 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg); in LowerCall()
3205 else if (RegVT.is128BitVector()) { in LowerCall()
3211 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg); in LowerCall()
3214 Arg = DAG.getBitcast(RegVT, Arg); in LowerCall()
15254 MVT RegVT = Op.getSimpleValueType(); in LowerExtendedLoad() local
15255 assert(RegVT.isVector() && "We only custom lower vector sext loads."); in LowerExtendedLoad()
15256 assert(RegVT.isInteger() && in LowerExtendedLoad()
15266 unsigned RegSz = RegVT.getSizeInBits(); in LowerExtendedLoad()
15272 assert(MemVT != RegVT && "Cannot extend to the same type"); in LowerExtendedLoad()
15275 unsigned NumElems = RegVT.getVectorNumElements(); in LowerExtendedLoad()
15305 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2); in LowerExtendedLoad()
15319 return DAG.getSExtOrTrunc(Load, dl, RegVT); in LowerExtendedLoad()
15403 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec); in LowerExtendedLoad()
15410 assert(TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND_VECTOR_INREG, RegVT) && in LowerExtendedLoad()
15413 SDValue Shuff = DAG.getSignExtendVectorInReg(SlicedVec, dl, RegVT); in LowerExtendedLoad()
15427 Shuff = DAG.getBitcast(RegVT, Shuff); in LowerExtendedLoad()
20181 auto RegVT = EVT::getVectorVT(*DAG.getContext(), ElemVT, in ReplaceNodeResults() local
20188 SDValue InVec0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, RegVT, Ops); in ReplaceNodeResults()
20190 SDValue InVec1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, RegVT, Ops); in ReplaceNodeResults()
20192 SDValue Res = DAG.getNode(X86ISD::AVG, dl, RegVT, InVec0, InVec1); in ReplaceNodeResults()
25905 EVT RegVT = Ld->getValueType(0); in PerformLOADCombine() local
25916 if (RegVT.is256BitVector() && !DCI.isBeforeLegalizeOps() && in PerformLOADCombine()
25918 TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), RegVT, in PerformLOADCombine()
25920 unsigned NumElems = RegVT.getVectorNumElements(); in PerformLOADCombine()
25943 SDValue NewVec = DAG.getUNDEF(RegVT); in PerformLOADCombine()