Lines Matching refs:VSRLI
4613 return ShiftRight ? DAG.getNode(X86ISD::VSRLI, dl, OpVT, WideSubVec, in Insert1BitVector()
4620 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits); in Insert1BitVector()
4633 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits); in Insert1BitVector()
7453 : (ByteShift ? X86ISD::VSRLDQ : X86ISD::VSRLI); in lowerVectorShuffleAsShift()
11576 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec, in ExtractBitFromMaskVector()
15989 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI) in getTargetVShiftByConstNode()
16014 case X86ISD::VSRLI: in getTargetVShiftByConstNode()
16064 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break; in getTargetVShiftNode()
18104 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG); in LowerMUL()
18105 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG); in LowerMUL()
18314 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI; in LowerScalarImmediateShift()
18337 getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt, DAG); in LowerScalarImmediateShift()
18392 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ShiftVT, in LowerScalarImmediateShift()
18483 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI; in LowerScalarVariableShift()
20512 case X86ISD::VSRLI: return "X86ISD::VSRLI"; in getTargetNodeName()