Lines Matching refs:v16i1
1316 addRegisterClass(MVT::v16i1, &X86::VK16RegClass); in X86TargetLowering()
1347 setOperationAction(ISD::LOAD, MVT::v16i1, Legal); in X86TargetLowering()
1373 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom); in X86TargetLowering()
1411 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i1, Custom); in X86TargetLowering()
1442 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom); in X86TargetLowering()
1472 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Custom); in X86TargetLowering()
1474 setOperationAction(ISD::SETCC, MVT::v16i1, Custom); in X86TargetLowering()
1480 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom); in X86TargetLowering()
1481 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v16i1, Custom); in X86TargetLowering()
1482 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom); in X86TargetLowering()
1485 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom); in X86TargetLowering()
1489 setOperationAction(ISD::SELECT, MVT::v16i1, Custom); in X86TargetLowering()
1878 case 16: return MVT::v16i1; in getSetCCResultType()
1901 case 16: return MVT::v16i1; in getSetCCResultType()
2724 else if (RegVT == MVT::v16i1) in LowerFormalArguments()
11202 case MVT::v16i1: in lower1BitVectorShuffle()
11572 rc = getRegClassFor(MVT::v16i1); in ExtractBitFromMaskVector()
16824 SDValue LHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
16825 SDValue RHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(2)); in LowerINTRINSIC_WO_CHAIN()