Lines Matching refs:v64i1
1623 addRegisterClass(MVT::v64i1, &X86::VK64RegClass); in X86TargetLowering()
1628 setOperationAction(ISD::SETCC, MVT::v64i1, Custom); in X86TargetLowering()
1637 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i1, Custom); in X86TargetLowering()
1641 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i1, Custom); in X86TargetLowering()
1647 setOperationAction(ISD::SELECT, MVT::v64i1, Custom); in X86TargetLowering()
1657 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i1, Custom); in X86TargetLowering()
1663 setOperationAction(ISD::TRUNCATE, MVT::v64i1, Custom); in X86TargetLowering()
1666 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i1, Custom); in X86TargetLowering()
1884 case 64: return MVT::v64i1; in getSetCCResultType()
2728 else if (RegVT == MVT::v64i1) in LowerFormalArguments()
11208 case MVT::v64i1: in lower1BitVectorShuffle()
16113 if (MaskVT == MVT::v64i1) { in getMaskNode()
16125 return DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v64i1, Lo, Hi); in getMaskNode()