Lines Matching refs:SrcReg2
2890 unsigned SrcReg2; in convertToThreeAddress() local
2893 SrcReg2, isKill2, isUndef2, ImplicitOp2)) in convertToThreeAddress()
2903 NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2); in convertToThreeAddress()
2910 LV->replaceKillInstruction(SrcReg2, MI, NewMI); in convertToThreeAddress()
4697 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, in analyzeCompare() argument
4709 SrcReg2 = 0; in analyzeCompare()
4719 SrcReg2 = 0; in analyzeCompare()
4728 SrcReg2 = MI->getOperand(2).getReg(); in analyzeCompare()
4740 SrcReg2 = 0; in analyzeCompare()
4749 SrcReg2 = MI->getOperand(1).getReg(); in analyzeCompare()
4760 SrcReg2 = 0; in analyzeCompare()
4775 unsigned SrcReg2, int ImmValue, in isRedundantFlagInstr() argument
4786 OI->getOperand(2).getReg() == SrcReg2) || in isRedundantFlagInstr()
4787 (OI->getOperand(1).getReg() == SrcReg2 && in isRedundantFlagInstr()
4920 optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, in optimizeCompareInstr() argument
4981 bool IsCmpZero = (SrcReg2 == 0 && CmpValue == 0); in optimizeCompareInstr()
5031 isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, Instr)) { in optimizeCompareInstr()
5058 bool IsSwapped = (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 && in optimizeCompareInstr()