Lines Matching refs:Latency

12 // Optimization Guide for AMD Family 16h Processors & Instruction Latency appendix.
81   def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; }
86      let Latency = !add(Lat, 3);
94   def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; }
99      let Latency = !add(Lat, 5);
114   let Latency = 6;
120   let Latency = 25;
124   let Latency = 41;
143 def : WriteRes<WriteLoad,  [JLAGU]> { let Latency = 5; }
178   let Latency = 21;
182   let Latency = 26;
187   let Latency = 19;
191   let Latency = 24;
201   let Latency = 2;
205   let Latency = 7;
219   let Latency = 2;
223   let Latency = 7;
229   let Latency = 1;
233   let Latency = 6;
238   let Latency = 3;
242   let Latency = 8;
253   let Latency = 7;
257   let Latency = 12;
263   let Latency = 13;
267   let Latency = 18;
273   let Latency = 6;
277   let Latency = 11;
283   let Latency = 13;
287   let Latency = 18;
296   let Latency = 3;
300   let Latency = 8;
305   let Latency = 2;
309   let Latency = 7;
314   let Latency = 2;
318   let Latency = 7;
327   let Latency = 2;
331   let Latency = 7;
336 def : WriteRes<WriteSystem,     [JAny]> { let Latency = 100; }
337 def : WriteRes<WriteMicrocoded, [JAny]> { let Latency = 100; }