Lines Matching refs:SI

1 ; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
4 ; SI-LABEL: {{^}}load_i8_to_f32:
5 ; SI: buffer_load_ubyte [[LOADREG:v[0-9]+]],
6 ; SI-NOT: bfe
7 ; SI-NOT: lshr
8 ; SI: v_cvt_f32_ubyte0_e32 [[CONV:v[0-9]+]], [[LOADREG]]
9 ; SI: buffer_store_dword [[CONV]],
17 ; SI-LABEL: {{^}}load_v2i8_to_v2f32:
18 ; SI: buffer_load_ushort [[LOADREG:v[0-9]+]],
19 ; SI-NOT: bfe
20 ; SI-NOT: lshr
21 ; SI-NOT: and
22 ; SI-DAG: v_cvt_f32_ubyte1_e32 v[[HIRESULT:[0-9]+]], [[LOADREG]]
23 ; SI-DAG: v_cvt_f32_ubyte0_e32 v[[LORESULT:[0-9]+]], [[LOADREG]]
24 ; SI: buffer_store_dwordx2 v{{\[}}[[LORESULT]]:[[HIRESULT]]{{\]}},
32 ; SI-LABEL: {{^}}load_v3i8_to_v3f32:
33 ; SI-NOT: bfe
34 ; SI-NOT: v_cvt_f32_ubyte3_e32
35 ; SI-DAG: v_cvt_f32_ubyte2_e32
36 ; SI-DAG: v_cvt_f32_ubyte1_e32
37 ; SI-DAG: v_cvt_f32_ubyte0_e32
38 ; SI: buffer_store_dwordx2 v{{\[}}[[LORESULT]]:[[HIRESULT]]{{\]}},
46 ; SI-LABEL: {{^}}load_v4i8_to_v4f32:
47 ; SI: buffer_load_dword [[LOADREG:v[0-9]+]]
48 ; SI-NOT: bfe
49 ; SI-NOT: lshr
50 ; SI-DAG: v_cvt_f32_ubyte3_e32 v[[HIRESULT:[0-9]+]], [[LOADREG]]
51 ; SI-DAG: v_cvt_f32_ubyte2_e32 v{{[0-9]+}}, [[LOADREG]]
52 ; SI-DAG: v_cvt_f32_ubyte1_e32 v{{[0-9]+}}, [[LOADREG]]
53 ; SI-DAG: v_cvt_f32_ubyte0_e32 v[[LORESULT:[0-9]+]], [[LOADREG]]
54 ; SI: buffer_store_dwordx4 v{{\[}}[[LORESULT]]:[[HIRESULT]]{{\]}},
65 ; SI-LABEL: {{^}}load_v4i8_to_v4f32_unaligned:
66 ; SI: buffer_load_ubyte [[LOADREG3:v[0-9]+]]
67 ; SI: buffer_load_ubyte [[LOADREG2:v[0-9]+]]
68 ; SI: buffer_load_ubyte [[LOADREG1:v[0-9]+]]
69 ; SI: buffer_load_ubyte [[LOADREG0:v[0-9]+]]
70 ; SI-NOT: v_lshlrev_b32
71 ; SI-NOT: v_or_b32
73 ; SI-DAG: v_cvt_f32_ubyte0_e32 v[[LORESULT:[0-9]+]], [[LOADREG0]]
74 ; SI-DAG: v_cvt_f32_ubyte0_e32 v{{[0-9]+}}, [[LOADREG1]]
75 ; SI-DAG: v_cvt_f32_ubyte0_e32 v{{[0-9]+}}, [[LOADREG2]]
76 ; SI-DAG: v_cvt_f32_ubyte0_e32 v[[HIRESULT:[0-9]+]], [[LOADREG3]]
78 ; SI: buffer_store_dwordx4 v{{\[}}[[LORESULT]]:[[HIRESULT]]{{\]}},
90 ; SI-LABEL: {{^}}load_v4i8_to_v4f32_2_uses:
91 ; SI: buffer_load_ubyte
92 ; SI: buffer_load_ubyte
93 ; SI: buffer_load_ubyte
94 ; SI: buffer_load_ubyte
95 ; SI: v_cvt_f32_ubyte0_e32
96 ; SI: v_cvt_f32_ubyte0_e32
97 ; SI: v_cvt_f32_ubyte0_e32
98 ; SI: v_cvt_f32_ubyte0_e32
106 ; SI: s_endpgm
117 ; SI-LABEL: {{^}}load_v7i8_to_v7f32:
118 ; SI: s_endpgm
126 ; SI-LABEL: {{^}}load_v8i8_to_v8f32:
127 ; SI: buffer_load_dwordx2 v{{\[}}[[LOLOAD:[0-9]+]]:[[HILOAD:[0-9]+]]{{\]}},
128 ; SI-NOT: bfe
129 ; SI-NOT: lshr
130 ; SI-DAG: v_cvt_f32_ubyte3_e32 v{{[0-9]+}}, v[[LOLOAD]]
131 ; SI-DAG: v_cvt_f32_ubyte2_e32 v{{[0-9]+}}, v[[LOLOAD]]
132 ; SI-DAG: v_cvt_f32_ubyte1_e32 v{{[0-9]+}}, v[[LOLOAD]]
133 ; SI-DAG: v_cvt_f32_ubyte0_e32 v{{[0-9]+}}, v[[LOLOAD]]
134 ; SI-DAG: v_cvt_f32_ubyte3_e32 v{{[0-9]+}}, v[[HILOAD]]
135 ; SI-DAG: v_cvt_f32_ubyte2_e32 v{{[0-9]+}}, v[[HILOAD]]
136 ; SI-DAG: v_cvt_f32_ubyte1_e32 v{{[0-9]+}}, v[[HILOAD]]
137 ; SI-DAG: v_cvt_f32_ubyte0_e32 v{{[0-9]+}}, v[[HILOAD]]
138 ; SI-NOT: bfe
139 ; SI-NOT: lshr
140 ; SI: buffer_store_dwordx4
141 ; SI: buffer_store_dwordx4
149 ; SI-LABEL: {{^}}i8_zext_inreg_i32_to_f32:
150 ; SI: buffer_load_dword [[LOADREG:v[0-9]+]],
151 ; SI: v_add_i32_e32 [[ADD:v[0-9]+]], vcc, 2, [[LOADREG]]
152 ; SI-NEXT: v_cvt_f32_ubyte0_e32 [[CONV:v[0-9]+]], [[ADD]]
153 ; SI: buffer_store_dword [[CONV]],
163 ; SI-LABEL: {{^}}i8_zext_inreg_hi1_to_f32: