Lines Matching refs:GCN

1 ; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -ch…
8 ; GCN-LABEL: {{^}}write_ds_sub0_offset0_global:
9 ; GCN: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 2, v0
10 ; GCN: v_sub_i32_e32 [[BASEPTR:v[0-9]+]], vcc, 0, [[SHL]]
11 ; GCN: v_mov_b32_e32 [[VAL:v[0-9]+]], 0x7b
12 ; GCN: ds_write_b32 [[BASEPTR]], [[VAL]] offset:12
23 ; GCN-LABEL: {{^}}add_x_shl_neg_to_sub_max_offset:
24 ; GCN-DAG: v_lshlrev_b32_e32 [[SCALED:v[0-9]+]], 2, v0
25 ; GCN-DAG: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0, [[SCALED]]
26 ; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 13
27 ; GCN: ds_write_b8 [[NEG]], [[K]] offset:65535
38 ; GCN-LABEL: {{^}}add_x_shl_neg_to_sub_max_offset_p1:
39 ; GCN-DAG: v_lshlrev_b32_e32 [[SCALED:v[0-9]+]], 2, v0
40 ; GCN-DAG: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0x10000, [[SCALED]]
41 ; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 13
42 ; GCN: ds_write_b8 [[NEG]], [[K]]{{$}}
53 ; GCN-LABEL: {{^}}add_x_shl_neg_to_sub_multi_use:
54 ; GCN-DAG: v_lshlrev_b32_e32 [[SCALED:v[0-9]+]], 2, v0
55 ; GCN-DAG: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0, [[SCALED]]
56 ; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 13
57 ; GCN-NOT: v_sub
58 ; GCN: ds_write_b32 [[NEG]], [[K]] offset:123{{$}}
59 ; GCN-NOT: v_sub
60 ; GCN: ds_write_b32 [[NEG]], [[K]] offset:456{{$}}
61 ; GCN: s_endpgm
75 ; GCN-LABEL: {{^}}add_x_shl_neg_to_sub_multi_use_same_offset:
76 ; GCN-DAG: v_lshlrev_b32_e32 [[SCALED:v[0-9]+]], 2, v0
77 ; GCN-DAG: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0, [[SCALED]]
78 ; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 13
79 ; GCN-NOT: v_sub
80 ; GCN: ds_write_b32 [[NEG]], [[K]] offset:123{{$}}
81 ; GCN-NOT: v_sub
82 ; GCN: ds_write_b32 [[NEG]], [[K]] offset:123{{$}}
83 ; GCN: s_endpgm
95 ; GCN-LABEL: {{^}}add_x_shl_neg_to_sub_misaligned_i64_max_offset:
96 ; GCN-DAG: v_lshlrev_b32_e32 [[SCALED:v[0-9]+]], 2, v0
97 ; GCN-DAG: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0, [[SCALED]]
98 ; GCN: ds_write2_b32 [[NEG]], {{v[0-9]+}}, {{v[0-9]+}} offset0:254 offset1:255
109 ; GCN-LABEL: {{^}}add_x_shl_neg_to_sub_misaligned_i64_max_offset_p1:
110 ; GCN-DAG: v_lshlrev_b32_e32 [[SCALED:v[0-9]+]], 2, v0
111 ; GCN-DAG: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0x3fc, [[SCALED]]
112 ; GCN: ds_write2_b32 [[NEG]], {{v[0-9]+}}, {{v[0-9]+}} offset1:1{{$}}