Lines Matching refs:SI

1 ; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs -enable-misched -asm-verbose < %s | FileChe…
5 ; SI-LABEL: @test_if
8 ; SI-NOT: s_mov_b64 s[{{[0-9]:[0-9]}}], -1
9 ; SI: v_mov_b32_e32 v{{[0-9]}}, -1
44 ; SI-LABEL: @simple_test_v_if
45 ; SI: v_cmp_ne_i32_e32 vcc, 0, v{{[0-9]+}}
46 ; SI: s_and_saveexec_b64 [[BR_SREG:s\[[0-9]+:[0-9]+\]]], vcc
47 ; SI: s_xor_b64 [[BR_SREG]], exec, [[BR_SREG]]
49 ; SI: ; BB#1
50 ; SI: buffer_store_dword
51 ; SI: s_endpgm
53 ; SI: BB1_2:
54 ; SI: s_or_b64 exec, exec, [[BR_SREG]]
55 ; SI: s_endpgm
70 ; SI-LABEL: @simple_test_v_loop
71 ; SI: v_cmp_ne_i32_e32 vcc, 0, v{{[0-9]+}}
72 ; SI: s_and_saveexec_b64 [[BR_SREG:s\[[0-9]+:[0-9]+\]]], vcc
73 ; SI: s_xor_b64 [[BR_SREG]], exec, [[BR_SREG]]
74 ; SI: s_cbranch_execz BB2_2
76 ; SI: ; BB#1:
77 ; SI: s_mov_b64 {{s\[[0-9]+:[0-9]+\]}}, 0{{$}}
79 ; SI: BB2_3:
80 ; SI: buffer_load_dword
81 ; SI-DAG: buffer_store_dword
82 ; SI-DAG: v_cmp_eq_i32_e32 vcc,
83 ; SI: s_or_b64 [[OR_SREG:s\[[0-9]+:[0-9]+\]]]
84 ; SI: s_andn2_b64 exec, exec, [[OR_SREG]]
85 ; SI: s_cbranch_execnz BB2_3
108 ; SI-LABEL: @multi_vcond_loop
112 ; SI: ; BB#0:
113 ; SI: buffer_load_dword [[VBOUND:v[0-9]+]]
114 ; SI: v_cmp_lt_i32_e32 vcc
115 ; SI: s_and_saveexec_b64 [[OUTER_CMP_SREG:s\[[0-9]+:[0-9]+\]]], vcc
116 ; SI: s_xor_b64 [[OUTER_CMP_SREG]], exec, [[OUTER_CMP_SREG]]
117 ; SI: s_cbranch_execz BB3_2
120 ; SI: ; BB#1:
121 ; SI: s_mov_b64 [[ZERO:s\[[0-9]+:[0-9]+\]]], 0{{$}}
122 ; SI: s_mov_b64 [[COND_STATE:s\[[0-9]+:[0-9]+\]]], [[ZERO]]
125 ; SI: BB3_3:
126 ; SI: buffer_load_dword [[B:v[0-9]+]]
127 ; SI: buffer_load_dword [[A:v[0-9]+]]
128 ; SI-DAG: v_cmp_ne_i32_e64 [[NEG1_CHECK_0:s\[[0-9]+:[0-9]+\]]], -1, [[A]]
129 ; SI-DAG: v_cmp_ne_i32_e32 [[NEG1_CHECK_1:vcc]], -1, [[B]]
130 ; SI: s_and_b64 [[ORNEG1:s\[[0-9]+:[0-9]+\]]], [[NEG1_CHECK_1]], [[NEG1_CHECK_0]]
131 ; SI: s_and_saveexec_b64 [[ORNEG2:s\[[0-9]+:[0-9]+\]]], [[ORNEG1]]
132 ; SI: s_xor_b64 [[ORNEG2]], exec, [[ORNEG2]]
133 ; SI: s_cbranch_execz BB3_5
135 ; SI: BB#4:
136 ; SI: buffer_store_dword
137 ; SI: v_cmp_ge_i64_e64 [[CMP:s\[[0-9]+:[0-9]+\]]]
138 ; SI: s_or_b64 [[COND_STATE]], [[CMP]], [[COND_STATE]]
140 ; SI: BB3_5:
141 ; SI: s_or_b64 exec, exec, [[ORNEG2]]
142 ; SI: s_or_b64 [[COND_STATE]], [[ORNEG2]], [[COND_STATE]]
143 ; SI: s_andn2_b64 exec, exec, [[COND_STATE]]
144 ; SI: s_cbranch_execnz BB3_3
146 ; SI: BB#6
147 ; SI: s_or_b64 exec, exec, [[COND_STATE]]
149 ; SI: BB3_2:
150 ; SI-NOT: [[COND_STATE]]
151 ; SI: s_endpgm