Lines Matching refs:addr1
6 ; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1
18 define void @simpleOneInstructionPromotion(<2 x i32>* %addr1, i32* %dest) {
19 %in1 = load <2 x i32>, <2 x i32>* %addr1, align 8
27 ; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1
37 define void @unsupportedInstructionForPromotion(<2 x i32>* %addr1, i32 %in2, i1* %dest) {
38 %in1 = load <2 x i32>, <2 x i32>* %addr1, align 8
47 ; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1
59 define void @unsupportedChainInDifferentBBs(<2 x i32>* %addr1, i32* %dest, i1 %bool) {
61 %in1 = load <2 x i32>, <2 x i32>* %addr1, align 8
73 ; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1
89 define void @chainOfInstructionsToPromote(<2 x i32>* %addr1, i32* %dest) {
90 %in1 = load <2 x i32>, <2 x i32>* %addr1, align 8
104 ; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1
114 define i32 @unsupportedMultiUses(<2 x i32>* %addr1, i32* %dest) {
115 %in1 = load <2 x i32>, <2 x i32>* %addr1, align 8
125 ; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1
135 define void @udivCase(<2 x i32>* %addr1, i32* %dest) {
136 %in1 = load <2 x i32>, <2 x i32>* %addr1, align 8
144 ; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1
154 define void @uremCase(<2 x i32>* %addr1, i32* %dest) {
155 %in1 = load <2 x i32>, <2 x i32>* %addr1, align 8
163 ; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1
173 define void @sdivCase(<2 x i32>* %addr1, i32* %dest) {
174 %in1 = load <2 x i32>, <2 x i32>* %addr1, align 8
182 ; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1
192 define void @sremCase(<2 x i32>* %addr1, i32* %dest) {
193 %in1 = load <2 x i32>, <2 x i32>* %addr1, align 8
201 ; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x float>, <2 x float>* %addr1
211 define void @fdivCase(<2 x float>* %addr1, float* %dest) {
212 %in1 = load <2 x float>, <2 x float>* %addr1, align 8
220 ; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x float>, <2 x float>* %addr1
230 define void @fremCase(<2 x float>* %addr1, float* %dest) {
231 %in1 = load <2 x float>, <2 x float>* %addr1, align 8
241 ; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1
246 define void @undefDivCase(<2 x i32>* %addr1, i32* %dest) {
247 %in1 = load <2 x i32>, <2 x i32>* %addr1, align 8
258 ; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1
263 define void @undefRemCase(<2 x i32>* %addr1, i32* %dest) {
264 %in1 = load <2 x i32>, <2 x i32>* %addr1, align 8
274 ; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x float>, <2 x float>* %addr1
284 define void @undefConstantFRemCaseWithFastMath(<2 x float>* %addr1, float* %dest) {
285 %in1 = load <2 x float>, <2 x float>* %addr1, align 8
295 ; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x float>, <2 x float>* %addr1
305 define void @undefVectorFRemCaseWithFastMath(<2 x float>* %addr1, float* %dest) {
306 %in1 = load <2 x float>, <2 x float>* %addr1, align 8
317 ; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x float>, <2 x float>* %addr1
327 define void @simpleOneInstructionPromotionFloat(<2 x float>* %addr1, float* %dest) {
328 %in1 = load <2 x float>, <2 x float>* %addr1, align 8
340 ; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1
350 define void @simpleOneInstructionPromotionVariableIdx(<2 x i32>* %addr1, i32* %dest, i32 %idx) {
351 %in1 = load <2 x i32>, <2 x i32>* %addr1, align 8
363 ; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <8 x i8>, <8 x i8>* %addr1
373 define void @simpleOneInstructionPromotion8x8(<8 x i8>* %addr1, i8* %dest) {
374 %in1 = load <8 x i8>, <8 x i8>* %addr1, align 8
384 ; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <4 x i32>, <4 x i32>* %addr1
397 define void @simpleOneInstructionPromotion4x32(<4 x i32>* %addr1, i32* %dest) {
398 %in1 = load <4 x i32>, <4 x i32>* %addr1, align 8