Lines Matching refs:PIC

13 ; RUN:             -check-prefix=32R1-LE -check-prefix=32R1-LE-PIC
17 ; RUN:             -check-prefix=32R2-LE -check-prefix=32R2-LE-PIC
21 ; RUN:             -check-prefix=32R6-LE -check-prefix=32R6-LE-PIC
27 ; RUN:             -check-prefix=32R1-BE -check-prefix=32R1-BE-PIC
31 ; RUN:             -check-prefix=32R2-BE -check-prefix=32R2-BE-PIC
35 ; RUN:             -check-prefix=32R6-BE -check-prefix=32R6-BE-PIC
55 ; 32R1-LE-PIC-DAG:    lw $[[R0:[0-9]+]], 0(${{[0-9]+}})
56 ; 32R1-LE-PIC-DAG:    lw $[[R1:[0-9]+]], 4(${{[0-9]+}})
57 ; 32R1-LE-PIC-DAG:    mtc1 $[[R0]], $f0
58 ; 32R1-LE-PIC-DAG:    mtc1 $[[R1]], $f1
60 ; 32R2-LE-PIC-DAG:    lw $[[R0:[0-9]+]], 0(${{[0-9]+}})
61 ; 32R2-LE-PIC-DAG:    lw $[[R1:[0-9]+]], 4(${{[0-9]+}})
62 ; 32R2-LE-PIC-DAG:    mtc1 $[[R0]], $f0
63 ; 32R2-LE-PIC-DAG:    mthc1 $[[R1]], $f0
65 ; 32R6-LE-PIC-DAG:    lw $[[R0:[0-9]+]], 0(${{[0-9]+}})
66 ; 32R6-LE-PIC-DAG:    lw $[[R1:[0-9]+]], 4(${{[0-9]+}})
67 ; 32R6-LE-PIC-DAG:    mtc1 $[[R0]], $f0
68 ; 32R6-LE-PIC-DAG:    mthc1 $[[R1]], $f0
91 ; 32R1-BE-PIC-DAG:    lw $[[R0:[0-9]+]], 0(${{[0-9]+}})
92 ; 32R1-BE-PIC-DAG:    lw $[[R1:[0-9]+]], 4(${{[0-9]+}})
93 ; 32R1-BE-PIC-DAG:    mtc1 $[[R1]], $f0
94 ; 32R1-BE-PIC-DAG:    mtc1 $[[R0]], $f1
96 ; 32R2-BE-PIC-DAG:    lw $[[R0:[0-9]+]], 0(${{[0-9]+}})
97 ; 32R2-BE-PIC-DAG:    lw $[[R1:[0-9]+]], 4(${{[0-9]+}})
98 ; 32R2-BE-PIC-DAG:    mtc1 $[[R1]], $f0
99 ; 32R2-BE-PIC-DAG:    mthc1 $[[R0]], $f0
101 ; 32R6-BE-PIC-DAG:    lw $[[R0:[0-9]+]], 0(${{[0-9]+}})
102 ; 32R6-BE-PIC-DAG:    lw $[[R1:[0-9]+]], 4(${{[0-9]+}})
103 ; 32R6-BE-PIC-DAG:    mtc1 $[[R1]], $f0
104 ; 32R6-BE-PIC-DAG:    mthc1 $[[R0]], $f0
120 ; 32R1-LE-PIC-DAG:    mfc1 $[[R0:[0-9]+]], $f12
121 ; 32R1-LE-PIC-DAG:    mfc1 $[[R1:[0-9]+]], $f13
122 ; 32R1-LE-PIC-DAG:    sw $[[R0]], 0(${{[0-9]+}})
123 ; 32R1-LE-PIC-DAG:    sw $[[R1]], 4(${{[0-9]+}})
125 ; 32R2-LE-PIC-DAG:    mfc1 $[[R0:[0-9]+]], $f12
126 ; 32R2-LE-PIC-DAG:    mfhc1 $[[R1:[0-9]+]], $f12
127 ; 32R2-LE-PIC-DAG:    sw $[[R0]], 0(${{[0-9]+}})
128 ; 32R2-LE-PIC-DAG:    sw $[[R1]], 4(${{[0-9]+}})
130 ; 32R6-LE-PIC-DAG:    mfc1 $[[R0:[0-9]+]], $f12
131 ; 32R6-LE-PIC-DAG:    mfhc1 $[[R1:[0-9]+]], $f12
132 ; 32R6-LE-PIC-DAG:    sw $[[R0]], 0(${{[0-9]+}})
133 ; 32R6-LE-PIC-DAG:    sw $[[R1]], 4(${{[0-9]+}})
156 ; 32R1-BE-PIC-DAG:    mfc1 $[[R0:[0-9]+]], $f12
157 ; 32R1-BE-PIC-DAG:    mfc1 $[[R1:[0-9]+]], $f13
158 ; 32R1-BE-PIC-DAG:    sw $[[R1]], 0(${{[0-9]+}})
159 ; 32R1-BE-PIC-DAG:    sw $[[R0]], 4(${{[0-9]+}})
161 ; 32R2-BE-PIC-DAG:    mfc1 $[[R0:[0-9]+]], $f12
162 ; 32R2-BE-PIC-DAG:    mfhc1 $[[R1:[0-9]+]], $f12
163 ; 32R2-BE-PIC-DAG:    sw $[[R1]], 0(${{[0-9]+}})
164 ; 32R2-BE-PIC-DAG:    sw $[[R0]], 4(${{[0-9]+}})
166 ; 32R6-BE-PIC-DAG:    mfc1 $[[R0:[0-9]+]], $f12
167 ; 32R6-BE-PIC-DAG:    mfhc1 $[[R1:[0-9]+]], $f12
168 ; 32R6-BE-PIC-DAG:    sw $[[R1]], 0(${{[0-9]+}})
169 ; 32R6-BE-PIC-DAG:    sw $[[R0]], 4(${{[0-9]+}})