Lines Matching refs:addr
21 %__a.addr.i31 = alloca i32, align 4
22 %__b.addr.i32 = alloca <4 x i32>*, align 8
23 %__a.addr.i29 = alloca i32, align 4
24 %__b.addr.i30 = alloca <4 x float>*, align 8
25 %__a.addr.i27 = alloca i32, align 4
26 %__b.addr.i28 = alloca <2 x i64>*, align 8
27 %__a.addr.i25 = alloca i32, align 4
28 %__b.addr.i26 = alloca <2 x i64>*, align 8
29 %__a.addr.i23 = alloca i32, align 4
30 %__b.addr.i24 = alloca <2 x double>*, align 8
31 %__a.addr.i20 = alloca <4 x i32>, align 16
32 %__b.addr.i21 = alloca i32, align 4
33 %__c.addr.i22 = alloca <4 x i32>*, align 8
34 %__a.addr.i17 = alloca <4 x i32>, align 16
35 %__b.addr.i18 = alloca i32, align 4
36 %__c.addr.i19 = alloca <4 x i32>*, align 8
37 %__a.addr.i14 = alloca <4 x float>, align 16
38 %__b.addr.i15 = alloca i32, align 4
39 %__c.addr.i16 = alloca <4 x float>*, align 8
40 %__a.addr.i11 = alloca <2 x i64>, align 16
41 %__b.addr.i12 = alloca i32, align 4
42 %__c.addr.i13 = alloca <2 x i64>*, align 8
43 %__a.addr.i8 = alloca <2 x i64>, align 16
44 %__b.addr.i9 = alloca i32, align 4
45 %__c.addr.i10 = alloca <2 x i64>*, align 8
46 %__a.addr.i6 = alloca <2 x double>, align 16
47 %__b.addr.i7 = alloca i32, align 4
48 %__c.addr.i = alloca <2 x double>*, align 8
49 %__a.addr.i = alloca i32, align 4
50 %__b.addr.i = alloca <4 x i32>*, align 8
51 store i32 0, i32* %__a.addr.i, align 4
52 store <4 x i32>* @vsi, <4 x i32>** %__b.addr.i, align 8
53 %0 = load i32, i32* %__a.addr.i, align 4
54 %1 = load <4 x i32>*, <4 x i32>** %__b.addr.i, align 8
59 store i32 0, i32* %__a.addr.i31, align 4
60 store <4 x i32>* @vui, <4 x i32>** %__b.addr.i32, align 8
61 %5 = load i32, i32* %__a.addr.i31, align 4
62 %6 = load <4 x i32>*, <4 x i32>** %__b.addr.i32, align 8
67 store i32 0, i32* %__a.addr.i29, align 4
68 store <4 x float>* @vf, <4 x float>** %__b.addr.i30, align 8
69 %10 = load i32, i32* %__a.addr.i29, align 4
70 %11 = load <4 x float>*, <4 x float>** %__b.addr.i30, align 8
76 store i32 0, i32* %__a.addr.i27, align 4
77 store <2 x i64>* @vsll, <2 x i64>** %__b.addr.i28, align 8
78 %16 = load i32, i32* %__a.addr.i27, align 4
79 %17 = load <2 x i64>*, <2 x i64>** %__b.addr.i28, align 8
85 store i32 0, i32* %__a.addr.i25, align 4
86 store <2 x i64>* @vull, <2 x i64>** %__b.addr.i26, align 8
87 %22 = load i32, i32* %__a.addr.i25, align 4
88 %23 = load <2 x i64>*, <2 x i64>** %__b.addr.i26, align 8
94 store i32 0, i32* %__a.addr.i23, align 4
95 store <2 x double>* @vd, <2 x double>** %__b.addr.i24, align 8
96 %28 = load i32, i32* %__a.addr.i23, align 4
97 %29 = load <2 x double>*, <2 x double>** %__b.addr.i24, align 8
103 store <4 x i32> %33, <4 x i32>* %__a.addr.i20, align 16
104 store i32 0, i32* %__b.addr.i21, align 4
105 store <4 x i32>* @res_vsi, <4 x i32>** %__c.addr.i22, align 8
106 %34 = load <4 x i32>, <4 x i32>* %__a.addr.i20, align 16
107 %35 = load i32, i32* %__b.addr.i21, align 4
108 %36 = load <4 x i32>*, <4 x i32>** %__c.addr.i22, align 8
113 store <4 x i32> %39, <4 x i32>* %__a.addr.i17, align 16
114 store i32 0, i32* %__b.addr.i18, align 4
115 store <4 x i32>* @res_vui, <4 x i32>** %__c.addr.i19, align 8
116 %40 = load <4 x i32>, <4 x i32>* %__a.addr.i17, align 16
117 %41 = load i32, i32* %__b.addr.i18, align 4
118 %42 = load <4 x i32>*, <4 x i32>** %__c.addr.i19, align 8
123 store <4 x float> %45, <4 x float>* %__a.addr.i14, align 16
124 store i32 0, i32* %__b.addr.i15, align 4
125 store <4 x float>* @res_vf, <4 x float>** %__c.addr.i16, align 8
126 %46 = load <4 x float>, <4 x float>* %__a.addr.i14, align 16
128 %48 = load i32, i32* %__b.addr.i15, align 4
129 %49 = load <4 x float>*, <4 x float>** %__c.addr.i16, align 8
134 store <2 x i64> %52, <2 x i64>* %__a.addr.i11, align 16
135 store i32 0, i32* %__b.addr.i12, align 4
136 store <2 x i64>* @res_vsll, <2 x i64>** %__c.addr.i13, align 8
137 %53 = load <2 x i64>, <2 x i64>* %__a.addr.i11, align 16
139 %55 = load i32, i32* %__b.addr.i12, align 4
140 %56 = load <2 x i64>*, <2 x i64>** %__c.addr.i13, align 8
145 store <2 x i64> %59, <2 x i64>* %__a.addr.i8, align 16
146 store i32 0, i32* %__b.addr.i9, align 4
147 store <2 x i64>* @res_vull, <2 x i64>** %__c.addr.i10, align 8
148 %60 = load <2 x i64>, <2 x i64>* %__a.addr.i8, align 16
150 %62 = load i32, i32* %__b.addr.i9, align 4
151 %63 = load <2 x i64>*, <2 x i64>** %__c.addr.i10, align 8
156 store <2 x double> %66, <2 x double>* %__a.addr.i6, align 16
157 store i32 0, i32* %__b.addr.i7, align 4
158 store <2 x double>* @res_vd, <2 x double>** %__c.addr.i, align 8
159 %67 = load <2 x double>, <2 x double>* %__a.addr.i6, align 16
160 %68 = load i32, i32* %__b.addr.i7, align 4
161 %69 = load <2 x double>*, <2 x double>** %__c.addr.i, align 8