Lines Matching refs:dbg
7 ; CHECK-NOT: llvm.dbg.declare
8 ; CHECK: llvm.dbg.value
9 ; CHECK: llvm.dbg.value
10 ; CHECK: llvm.dbg.value
11 ; CHECK: llvm.dbg.value
12 ; CHECK: llvm.dbg.value
14 define i32 @f(i32 %a, i32 %b) nounwind ssp !dbg !1 {
20 call void @llvm.dbg.declare(metadata i32* %a.addr, metadata !6, metadata !DIExpression()), !dbg !7
22 call void @llvm.dbg.declare(metadata i32* %b.addr, metadata !8, metadata !DIExpression()), !dbg !9
23 call void @llvm.dbg.declare(metadata i32* %c, metadata !10, metadata !DIExpression()), !dbg !12
24 %tmp = load i32, i32* %a.addr, align 4, !dbg !13
25 store i32 %tmp, i32* %c, align 4, !dbg !13
26 %tmp1 = load i32, i32* %a.addr, align 4, !dbg !14
27 %tmp2 = load i32, i32* %b.addr, align 4, !dbg !14
28 %add = add nsw i32 %tmp1, %tmp2, !dbg !14
29 store i32 %add, i32* %a.addr, align 4, !dbg !14
30 %tmp3 = load i32, i32* %c, align 4, !dbg !15
31 %tmp4 = load i32, i32* %b.addr, align 4, !dbg !15
32 %sub = sub nsw i32 %tmp3, %tmp4, !dbg !15
33 store i32 %sub, i32* %b.addr, align 4, !dbg !15
34 %tmp5 = load i32, i32* %a.addr, align 4, !dbg !16
35 %tmp6 = load i32, i32* %b.addr, align 4, !dbg !16
36 %add7 = add nsw i32 %tmp5, %tmp6, !dbg !16
37 ret i32 %add7, !dbg !16
40 declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone
42 !llvm.dbg.cu = !{!0}