Lines Matching refs:ProcModel
416 const CodeGenProcModel &ProcModel) const { in expandRWSeqForProc()
425 if (&getProcModel(ModelDef) != &ProcModel) in expandRWSeqForProc()
430 "defined for processor " + ProcModel.ModelName + in expandRWSeqForProc()
436 RWSeq, IsRead,ProcModel); in expandRWSeqForProc()
448 expandRWSeqForProc(*I, RWSeq, IsRead, ProcModel); in expandRWSeqForProc()
556 const CodeGenProcModel &ProcModel = in collectSchedClasses() local
558 ProcIndices.push_back(ProcModel.Index); in collectSchedClasses()
559 dbgs() << "InstRW on " << ProcModel.ModelName << " for " << InstName; in collectSchedClasses()
771 for (CodeGenProcModel &ProcModel : ProcModels) { in collectProcItins()
772 if (!ProcModel.hasItineraries()) in collectProcItins()
775 RecVec ItinRecords = ProcModel.ItinsDef->getValueAsListOfDefs("IID"); in collectProcItins()
779 ProcModel.ItinDefList.resize(NumInstrSchedClasses); in collectProcItins()
791 ProcModel.ItinDefList[SCI->Index] = ItinData; in collectProcItins()
796 DEBUG(dbgs() << ProcModel.ItinsDef->getName() in collectProcItins()
801 assert(!ProcModel.ItinDefList[0] && "NoItinerary class can't have rec"); in collectProcItins()
803 for (unsigned i = 1, N = ProcModel.ItinDefList.size(); i < N; ++i) { in collectProcItins()
804 if (!ProcModel.ItinDefList[i]) in collectProcItins()
805 dbgs() << ProcModel.ItinsDef->getName() in collectProcItins()