Lines Matching refs:OS
61 void EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
63 void emitComposeSubRegIndices(raw_ostream &OS, CodeGenRegBank &RegBank,
65 void emitComposeSubRegIndexLaneMask(raw_ostream &OS, CodeGenRegBank &RegBank,
71 void RegisterInfoEmitter::runEnums(raw_ostream &OS, in runEnums() argument
81 emitSourceFileHeader("Target Register Enum Values", OS); in runEnums()
83 OS << "\n#ifdef GET_REGINFO_ENUM\n"; in runEnums()
84 OS << "#undef GET_REGINFO_ENUM\n"; in runEnums()
86 OS << "namespace llvm {\n\n"; in runEnums()
88 OS << "class MCRegisterClass;\n" in runEnums()
93 OS << "namespace " << Namespace << " {\n"; in runEnums()
94 OS << "enum {\n NoRegister,\n"; in runEnums()
97 OS << " " << Reg.getName() << " = " << Reg.EnumValue << ",\n"; in runEnums()
100 OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n"; in runEnums()
101 OS << "};\n"; in runEnums()
103 OS << "}\n"; in runEnums()
112 OS << "\n// Register classes\n"; in runEnums()
114 OS << "namespace " << Namespace << " {\n"; in runEnums()
115 OS << "enum {\n"; in runEnums()
117 OS << " " << RC.getName() << "RegClassID" in runEnums()
119 OS << "\n };\n"; in runEnums()
121 OS << "}\n"; in runEnums()
128 OS << "\n// Register alternate name indices\n"; in runEnums()
130 OS << "namespace " << Namespace << " {\n"; in runEnums()
131 OS << "enum {\n"; in runEnums()
133 OS << " " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n"; in runEnums()
134 OS << " NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n"; in runEnums()
135 OS << "};\n"; in runEnums()
137 OS << "}\n"; in runEnums()
142 OS << "\n// Subregister indices\n"; in runEnums()
145 OS << "namespace " << Namespace << " {\n"; in runEnums()
146 OS << "enum {\n NoSubRegister,\n"; in runEnums()
149 OS << " " << Idx.getName() << ",\t// " << ++i << "\n"; in runEnums()
150 OS << " NUM_TARGET_SUBREGS\n};\n"; in runEnums()
152 OS << "}\n"; in runEnums()
155 OS << "} // End llvm namespace\n"; in runEnums()
156 OS << "#endif // GET_REGINFO_ENUM\n\n"; in runEnums()
159 static void printInt(raw_ostream &OS, int Val) { in printInt() argument
160 OS << Val; in printInt()
173 EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank, in EmitRegUnitPressure() argument
178 OS << "/// Get the weight in units of pressure for this register class.\n" in EmitRegUnitPressure()
185 OS << " {0, 0"; in EmitRegUnitPressure()
189 OS << " {" << (*Regs.begin())->getWeight(RegBank) in EmitRegUnitPressure()
192 OS << "}, \t// " << RC.getName() << "\n"; in EmitRegUnitPressure()
194 OS << " };\n" in EmitRegUnitPressure()
206 OS << "/// Get the weight in units of pressure for this register unit.\n" in EmitRegUnitPressure()
212 OS << " static const uint8_t RUWeightTable[] = {\n "; in EmitRegUnitPressure()
217 OS << RU.Weight << ", "; in EmitRegUnitPressure()
219 OS << "};\n" in EmitRegUnitPressure()
223 OS << " // All register units have unit weight.\n" in EmitRegUnitPressure()
226 OS << "}\n\n"; in EmitRegUnitPressure()
228 OS << "\n" in EmitRegUnitPressure()
233 OS << "// Get the name of this register unit pressure set.\n" in EmitRegUnitPressure()
241 OS << " \"" << RegUnits.Name << "\",\n"; in EmitRegUnitPressure()
243 OS << " };\n" in EmitRegUnitPressure()
247 OS << "// Get the register unit pressure limit for this dimension.\n" in EmitRegUnitPressure()
255 OS << " " << RegUnits.Weight << ", \t// " << i << ": " in EmitRegUnitPressure()
258 OS << " };\n" in EmitRegUnitPressure()
282 OS << "/// Table of pressure sets per register class or unit.\n" in EmitRegUnitPressure()
284 PSetsSeqs.emit(OS, printInt, "-1"); in EmitRegUnitPressure()
285 OS << "};\n\n"; in EmitRegUnitPressure()
287 OS << "/// Get the dimensions of register pressure impacted by this " in EmitRegUnitPressure()
292 OS << " static const " << getMinimalTypeForRange(PSetsSeqs.size()-1) in EmitRegUnitPressure()
295 OS << PSetsSeqs.get(PSets[i]) << ","; in EmitRegUnitPressure()
297 OS << "};\n" in EmitRegUnitPressure()
301 OS << "/// Get the dimensions of register pressure impacted by this " in EmitRegUnitPressure()
308 OS << " static const " << getMinimalTypeForRange(PSetsSeqs.size()-1) in EmitRegUnitPressure()
312 OS << PSetsSeqs.get(PSets[RegBank.getRegUnit(UnitIdx).RegClassUnitSetsIdx]) in EmitRegUnitPressure()
315 OS << "};\n" in EmitRegUnitPressure()
321 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { in EmitRegMappingTables() argument
349 OS << "// " << Namespace << " Dwarf<->LLVM register mappings.\n"; in EmitRegMappingTables()
354 OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace; in EmitRegMappingTables()
355 OS << (j == 0 ? "DwarfFlavour" : "EHFlavour"); in EmitRegMappingTables()
356 OS << i << "Dwarf2L[]"; in EmitRegMappingTables()
359 OS << " = {\n"; in EmitRegMappingTables()
374 OS << " { " << I->first << "U, " << getQualifiedName(I->second) in EmitRegMappingTables()
377 OS << "};\n"; in EmitRegMappingTables()
379 OS << ";\n"; in EmitRegMappingTables()
384 OS << "extern const unsigned " << Namespace in EmitRegMappingTables()
387 OS << " = array_lengthof(" << Namespace in EmitRegMappingTables()
391 OS << ";\n\n"; in EmitRegMappingTables()
409 OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace; in EmitRegMappingTables()
410 OS << (j == 0 ? "DwarfFlavour" : "EHFlavour"); in EmitRegMappingTables()
411 OS << i << "L2Dwarf[]"; in EmitRegMappingTables()
413 OS << " = {\n"; in EmitRegMappingTables()
422 OS << " { " << getQualifiedName(I->first) << ", " << RegNo in EmitRegMappingTables()
425 OS << "};\n"; in EmitRegMappingTables()
427 OS << ";\n"; in EmitRegMappingTables()
432 OS << "extern const unsigned " << Namespace in EmitRegMappingTables()
435 OS << " = array_lengthof(" << Namespace in EmitRegMappingTables()
438 OS << ";\n\n"; in EmitRegMappingTables()
444 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { in EmitRegMapping() argument
461 OS << " switch ("; in EmitRegMapping()
463 OS << "DwarfFlavour"; in EmitRegMapping()
465 OS << "EHFlavour"; in EmitRegMapping()
466 OS << ") {\n" in EmitRegMapping()
471 OS << " case " << i << ":\n"; in EmitRegMapping()
472 OS << " "; in EmitRegMapping()
474 OS << "RI->"; in EmitRegMapping()
479 OS << "mapDwarfRegsToLLVMRegs(" << Tmp << ", " << Tmp << "Size, "; in EmitRegMapping()
481 OS << "false"; in EmitRegMapping()
483 OS << "true"; in EmitRegMapping()
484 OS << ");\n"; in EmitRegMapping()
485 OS << " break;\n"; in EmitRegMapping()
487 OS << " }\n"; in EmitRegMapping()
492 OS << " switch ("; in EmitRegMapping()
494 OS << "DwarfFlavour"; in EmitRegMapping()
496 OS << "EHFlavour"; in EmitRegMapping()
497 OS << ") {\n" in EmitRegMapping()
502 OS << " case " << i << ":\n"; in EmitRegMapping()
503 OS << " "; in EmitRegMapping()
505 OS << "RI->"; in EmitRegMapping()
510 OS << "mapLLVMRegsToDwarfRegs(" << Tmp << ", " << Tmp << "Size, "; in EmitRegMapping()
512 OS << "false"; in EmitRegMapping()
514 OS << "true"; in EmitRegMapping()
515 OS << ");\n"; in EmitRegMapping()
516 OS << " break;\n"; in EmitRegMapping()
518 OS << " }\n"; in EmitRegMapping()
524 static void printBitVectorAsHex(raw_ostream &OS, in printBitVectorAsHex() argument
533 OS << format("0x%0*x, ", Digits, Value); in printBitVectorAsHex()
547 void print(raw_ostream &OS) { in print() argument
548 printBitVectorAsHex(OS, Values, 8); in print()
552 static void printSimpleValueType(raw_ostream &OS, MVT::SimpleValueType VT) { in printSimpleValueType() argument
553 OS << getEnumName(VT); in printSimpleValueType()
556 static void printSubRegIndex(raw_ostream &OS, const CodeGenSubRegIndex *Idx) { in printSubRegIndex() argument
557 OS << Idx->EnumValue; in printSubRegIndex()
600 static void printDiff16(raw_ostream &OS, uint16_t Val) { in printDiff16() argument
601 OS << Val; in printDiff16()
604 static void printMask(raw_ostream &OS, unsigned Val) { in printMask() argument
605 OS << format("0x%08X", Val); in printMask()
630 RegisterInfoEmitter::emitComposeSubRegIndices(raw_ostream &OS, in emitComposeSubRegIndices() argument
634 OS << "unsigned " << ClName in emitComposeSubRegIndices()
669 OS << " static const " << getMinimalTypeForRange(Rows.size()) << " RowMap[" in emitComposeSubRegIndices()
672 OS << RowMap[i] << ", "; in emitComposeSubRegIndices()
673 OS << "\n };\n"; in emitComposeSubRegIndices()
677 OS << " static const " << getMinimalTypeForRange(SubRegIndicesSize + 1) in emitComposeSubRegIndices()
680 OS << " { "; in emitComposeSubRegIndices()
683 OS << Rows[r][i]->EnumValue << ", "; in emitComposeSubRegIndices()
685 OS << "0, "; in emitComposeSubRegIndices()
686 OS << "},\n"; in emitComposeSubRegIndices()
688 OS << " };\n\n"; in emitComposeSubRegIndices()
690 OS << " --IdxA; assert(IdxA < " << SubRegIndicesSize << ");\n" in emitComposeSubRegIndices()
693 OS << " return Rows[RowMap[IdxA]][IdxB];\n"; in emitComposeSubRegIndices()
695 OS << " return Rows[0][IdxB];\n"; in emitComposeSubRegIndices()
696 OS << "}\n\n"; in emitComposeSubRegIndices()
700 RegisterInfoEmitter::emitComposeSubRegIndexLaneMask(raw_ostream &OS, in emitComposeSubRegIndexLaneMask() argument
731 OS << "unsigned " << ClName in emitComposeSubRegIndexLaneMask()
735 OS << " struct MaskRolOp {\n" in emitComposeSubRegIndexLaneMask()
742 OS << " "; in emitComposeSubRegIndexLaneMask()
746 OS << format("{ 0x%08X, %2u }, ", P.Mask, P.RotateLeft); in emitComposeSubRegIndexLaneMask()
748 OS << "{ 0, 0 }"; in emitComposeSubRegIndexLaneMask()
750 OS << ", "; in emitComposeSubRegIndexLaneMask()
751 OS << " // Sequence " << Idx << "\n"; in emitComposeSubRegIndexLaneMask()
754 OS << " };\n" in emitComposeSubRegIndexLaneMask()
757 OS << " "; in emitComposeSubRegIndexLaneMask()
759 OS << format("&Seqs[%u]", Idx); in emitComposeSubRegIndexLaneMask()
761 OS << ","; in emitComposeSubRegIndexLaneMask()
762 OS << " // to " << SubRegIndices[i].getName() << "\n"; in emitComposeSubRegIndexLaneMask()
764 OS << " };\n\n"; in emitComposeSubRegIndexLaneMask()
766 OS << " --IdxA; assert(IdxA < " << SubRegIndices.size() in emitComposeSubRegIndexLaneMask()
783 RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, in runMCDesc() argument
785 emitSourceFileHeader("MC Register Information", OS); in runMCDesc()
787 OS << "\n#ifdef GET_REGINFO_MC_DESC\n"; in runMCDesc()
788 OS << "#undef GET_REGINFO_MC_DESC\n"; in runMCDesc()
884 OS << "namespace llvm {\n\n"; in runMCDesc()
889 OS << "extern const MCPhysReg " << TargetName << "RegDiffLists[] = {\n"; in runMCDesc()
890 DiffSeqs.emit(OS, printDiff16); in runMCDesc()
891 OS << "};\n\n"; in runMCDesc()
894 OS << "extern const unsigned " << TargetName << "LaneMaskLists[] = {\n"; in runMCDesc()
895 LaneMaskSeqs.emit(OS, printMask, "~0u"); in runMCDesc()
896 OS << "};\n\n"; in runMCDesc()
899 OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[] = {\n"; in runMCDesc()
900 SubRegIdxSeqs.emit(OS, printSubRegIndex); in runMCDesc()
901 OS << "};\n\n"; in runMCDesc()
904 OS << "extern const MCRegisterInfo::SubRegCoveredBits " in runMCDesc()
906 OS << " { " << (uint16_t)-1 << ", " << (uint16_t)-1 << " },\n"; in runMCDesc()
908 OS << " { " << Idx.Offset << ", " << Idx.Size << " },\t// " in runMCDesc()
911 OS << "};\n\n"; in runMCDesc()
915 OS << "extern const char " << TargetName << "RegStrings[] = {\n"; in runMCDesc()
916 RegStrings.emit(OS, printChar); in runMCDesc()
917 OS << "};\n\n"; in runMCDesc()
919 OS << "extern const MCRegisterDesc " << TargetName in runMCDesc()
921 OS << " { " << RegStrings.get("") << ", 0, 0, 0, 0, 0 },\n"; in runMCDesc()
926 OS << " { " << RegStrings.get(Reg.getName()) << ", " in runMCDesc()
933 OS << "};\n\n"; // End of register descriptors... in runMCDesc()
937 OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2] = {\n"; in runMCDesc()
942 OS << " { " << getQualifiedName(Roots.front()->TheDef); in runMCDesc()
944 OS << ", " << getQualifiedName(Roots[r]->TheDef); in runMCDesc()
945 OS << " },\n"; in runMCDesc()
947 OS << "};\n\n"; in runMCDesc()
952 OS << "namespace { // Register classes...\n"; in runMCDesc()
966 OS << " // " << Name << " Register Class...\n" in runMCDesc()
971 OS << getQualifiedName(Reg) << ", "; in runMCDesc()
973 OS << "\n };\n\n"; in runMCDesc()
975 OS << " // " << Name << " Bit set.\n" in runMCDesc()
983 BVE.print(OS); in runMCDesc()
984 OS << "\n };\n\n"; in runMCDesc()
987 OS << "}\n\n"; in runMCDesc()
990 OS << "extern const char " << TargetName << "RegClassStrings[] = {\n"; in runMCDesc()
991 RegClassStrings.emit(OS, printChar); in runMCDesc()
992 OS << "};\n\n"; in runMCDesc()
994 OS << "extern const MCRegisterClass " << TargetName in runMCDesc()
1004 OS << " { " << RC.getName() << ", " << RC.getName() << "Bits, " in runMCDesc()
1014 OS << "};\n\n"; in runMCDesc()
1016 EmitRegMappingTables(OS, Regs, false); in runMCDesc()
1019 OS << "extern const uint16_t " << TargetName; in runMCDesc()
1020 OS << "RegEncodingTable[] = {\n"; in runMCDesc()
1022 OS << " 0,\n"; in runMCDesc()
1031 OS << " " << Value << ",\n"; in runMCDesc()
1033 OS << "};\n"; // End of HW encoding table in runMCDesc()
1036 OS << "static inline void Init" << TargetName in runMCDesc()
1050 EmitRegMapping(OS, Regs, false); in runMCDesc()
1052 OS << "}\n\n"; in runMCDesc()
1054 OS << "} // End llvm namespace\n"; in runMCDesc()
1055 OS << "#endif // GET_REGINFO_MC_DESC\n\n"; in runMCDesc()
1059 RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target, in runTargetHeader() argument
1061 emitSourceFileHeader("Register Information Header Fragment", OS); in runTargetHeader()
1063 OS << "\n#ifdef GET_REGINFO_HEADER\n"; in runTargetHeader()
1064 OS << "#undef GET_REGINFO_HEADER\n"; in runTargetHeader()
1069 OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n\n"; in runTargetHeader()
1071 OS << "namespace llvm {\n\n"; in runTargetHeader()
1073 OS << "class " << TargetName << "FrameLowering;\n\n"; in runTargetHeader()
1075 OS << "struct " << ClassName << " : public TargetRegisterInfo {\n" in runTargetHeader()
1079 OS << " unsigned composeSubRegIndicesImpl" in runTargetHeader()
1086 OS << " const RegClassWeight &getRegClassWeight(" in runTargetHeader()
1107 OS << "namespace " << RegisterClasses.front().Namespace in runTargetHeader()
1114 OS << " extern const TargetRegisterClass " << Name << "RegClass;\n"; in runTargetHeader()
1116 OS << "} // end of namespace " << TargetName << "\n\n"; in runTargetHeader()
1118 OS << "} // End llvm namespace\n"; in runTargetHeader()
1119 OS << "#endif // GET_REGINFO_HEADER\n\n"; in runTargetHeader()
1126 RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, in runTargetDesc() argument
1128 emitSourceFileHeader("Target Register and Register Classes Information", OS); in runTargetDesc()
1130 OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n"; in runTargetDesc()
1131 OS << "#undef GET_REGINFO_TARGET_DESC\n"; in runTargetDesc()
1133 OS << "namespace llvm {\n\n"; in runTargetDesc()
1136 OS << "extern const MCRegisterClass " << Target.getName() in runTargetDesc()
1159 OS << "\nstatic const MVT::SimpleValueType VTLists[] = {\n"; in runTargetDesc()
1160 VTSeqs.emit(OS, printSimpleValueType, "MVT::Other"); in runTargetDesc()
1161 OS << "};\n"; in runTargetDesc()
1164 OS << "\nstatic const char *const SubRegIndexNameTable[] = { \""; in runTargetDesc()
1167 OS << Idx.getName(); in runTargetDesc()
1168 OS << "\", \""; in runTargetDesc()
1170 OS << "\" };\n\n"; in runTargetDesc()
1173 OS << "\nstatic const unsigned SubRegIndexLaneMaskTable[] = {\n ~0u,\n"; in runTargetDesc()
1175 OS << format(" 0x%08x, // ", Idx.LaneMask) << Idx.getName() << '\n'; in runTargetDesc()
1177 OS << " };\n\n"; in runTargetDesc()
1179 OS << "\n"; in runTargetDesc()
1183 OS << "\nstatic const TargetRegisterClass *const " in runTargetDesc()
1211 OS << "static const uint32_t " << RC.getName() << "SubClassMask[] = {\n "; in runTargetDesc()
1212 printBitVectorAsHex(OS, RC.getSubClasses(), 32); in runTargetDesc()
1223 OS << "\n "; in runTargetDesc()
1224 printBitVectorAsHex(OS, MaskBV, 32); in runTargetDesc()
1225 OS << "// " << Idx.getName(); in runTargetDesc()
1228 OS << "\n};\n\n"; in runTargetDesc()
1231 OS << "static const uint16_t SuperRegIdxSeqs[] = {\n"; in runTargetDesc()
1233 SuperRegIdxSeqs.emit(OS, printSubRegIndex); in runTargetDesc()
1234 OS << "};\n\n"; in runTargetDesc()
1244 OS << "static const TargetRegisterClass *const " in runTargetDesc()
1247 OS << " &" << Super->getQualifiedName() << "RegClass,\n"; in runTargetDesc()
1248 OS << " nullptr\n};\n\n"; in runTargetDesc()
1254 OS << "\nstatic inline unsigned " << RC.getName() in runTargetDesc()
1262 OS << " static const MCPhysReg AltOrder" << oi << "[] = {"; in runTargetDesc()
1264 OS << (elem ? ", " : " ") << getQualifiedName(Elems[elem]); in runTargetDesc()
1265 OS << " };\n"; in runTargetDesc()
1268 OS << " const MCRegisterClass &MCR = " << Target.getName() in runTargetDesc()
1274 OS << "),\n ArrayRef<MCPhysReg>("; in runTargetDesc()
1276 OS << "),\n makeArrayRef(AltOrder" << oi; in runTargetDesc()
1277 OS << ")\n };\n const unsigned Select = " << RC.getName() in runTargetDesc()
1284 OS << "\nnamespace " << RegisterClasses.front().Namespace in runTargetDesc()
1288 OS << " extern const TargetRegisterClass " << RC.getName() in runTargetDesc()
1299 OS << "NullRegClasses,\n "; in runTargetDesc()
1301 OS << RC.getName() << "Superclasses,\n "; in runTargetDesc()
1303 OS << "nullptr\n"; in runTargetDesc()
1305 OS << RC.getName() << "GetRawAllocationOrder\n"; in runTargetDesc()
1306 OS << " };\n\n"; in runTargetDesc()
1309 OS << "}\n"; in runTargetDesc()
1312 OS << "\nnamespace {\n"; in runTargetDesc()
1313 OS << " const TargetRegisterClass* const RegisterClasses[] = {\n"; in runTargetDesc()
1315 OS << " &" << RC.getQualifiedName() << "RegClass,\n"; in runTargetDesc()
1316 OS << " };\n"; in runTargetDesc()
1317 OS << "}\n"; // End of anonymous namespace... in runTargetDesc()
1321 OS << "\nstatic const TargetRegisterInfoDesc " in runTargetDesc()
1323 OS << " { 0, 0 },\n"; in runTargetDesc()
1327 OS << " { "; in runTargetDesc()
1328 OS << Reg.CostPerUse << ", " in runTargetDesc()
1331 OS << "};\n"; // End of register descriptors... in runTargetDesc()
1340 emitComposeSubRegIndices(OS, RegBank, ClassName); in runTargetDesc()
1341 emitComposeSubRegIndexLaneMask(OS, RegBank, ClassName); in runTargetDesc()
1346 OS << "const TargetRegisterClass *" << ClassName in runTargetDesc()
1352 OS << " static const uint8_t Table["; in runTargetDesc()
1354 OS << " static const uint16_t Table["; in runTargetDesc()
1357 OS << RegisterClasses.size() << "][" << SubRegIndicesSize << "] = {\n"; in runTargetDesc()
1359 OS << " {\t// " << RC.getName() << "\n"; in runTargetDesc()
1362 OS << " " << SRC->EnumValue + 1 << ",\t// " << Idx.getName() in runTargetDesc()
1365 OS << " 0,\t// " << Idx.getName() << "\n"; in runTargetDesc()
1367 OS << " },\n"; in runTargetDesc()
1369 OS << " };\n assert(RC && \"Missing regclass\");\n" in runTargetDesc()
1376 EmitRegUnitPressure(OS, RegBank, ClassName); in runTargetDesc()
1379 OS << "extern const MCRegisterDesc " << TargetName << "RegDesc[];\n"; in runTargetDesc()
1380 OS << "extern const MCPhysReg " << TargetName << "RegDiffLists[];\n"; in runTargetDesc()
1381 OS << "extern const unsigned " << TargetName << "LaneMaskLists[];\n"; in runTargetDesc()
1382 OS << "extern const char " << TargetName << "RegStrings[];\n"; in runTargetDesc()
1383 OS << "extern const char " << TargetName << "RegClassStrings[];\n"; in runTargetDesc()
1384 OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2];\n"; in runTargetDesc()
1385 OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[];\n"; in runTargetDesc()
1386 OS << "extern const MCRegisterInfo::SubRegCoveredBits " in runTargetDesc()
1388 OS << "extern const uint16_t " << TargetName << "RegEncodingTable[];\n"; in runTargetDesc()
1390 EmitRegMappingTables(OS, Regs, true); in runTargetDesc()
1392 OS << ClassName << "::\n" << ClassName in runTargetDesc()
1397 OS.write_hex(RegBank.CoveringLanes); in runTargetDesc()
1398 OS << ") {\n" in runTargetDesc()
1413 EmitRegMapping(OS, Regs, true); in runTargetDesc()
1415 OS << "}\n\n"; in runTargetDesc()
1427 OS << "static const MCPhysReg " << CSRSet->getName() in runTargetDesc()
1430 OS << getQualifiedName((*Regs)[r]) << ", "; in runTargetDesc()
1431 OS << "0 };\n"; in runTargetDesc()
1446 OS << "static const uint32_t " << CSRSet->getName() in runTargetDesc()
1448 printBitVectorAsHex(OS, Covered, 32); in runTargetDesc()
1449 OS << "};\n"; in runTargetDesc()
1451 OS << "\n\n"; in runTargetDesc()
1453 OS << "ArrayRef<const uint32_t *> " << ClassName in runTargetDesc()
1456 OS << " static const uint32_t *const Masks[] = {\n"; in runTargetDesc()
1458 OS << " " << CSRSet->getName() << "_RegMask,\n"; in runTargetDesc()
1459 OS << " };\n"; in runTargetDesc()
1460 OS << " return makeArrayRef(Masks);\n"; in runTargetDesc()
1462 OS << " return None;\n"; in runTargetDesc()
1464 OS << "}\n\n"; in runTargetDesc()
1466 OS << "ArrayRef<const char *> " << ClassName in runTargetDesc()
1469 OS << " static const char *const Names[] = {\n"; in runTargetDesc()
1471 OS << " " << '"' << CSRSet->getName() << '"' << ",\n"; in runTargetDesc()
1472 OS << " };\n"; in runTargetDesc()
1473 OS << " return makeArrayRef(Names);\n"; in runTargetDesc()
1475 OS << " return None;\n"; in runTargetDesc()
1477 OS << "}\n\n"; in runTargetDesc()
1479 OS << "const " << TargetName << "FrameLowering *\n" << TargetName in runTargetDesc()
1485 OS << "} // End llvm namespace\n"; in runTargetDesc()
1486 OS << "#endif // GET_REGINFO_TARGET_DESC\n\n"; in runTargetDesc()
1489 void RegisterInfoEmitter::run(raw_ostream &OS) { in run() argument
1494 runEnums(OS, Target, RegBank); in run()
1495 runMCDesc(OS, Target, RegBank); in run()
1496 runTargetHeader(OS, Target, RegBank); in run()
1497 runTargetDesc(OS, Target, RegBank); in run()
1502 void EmitRegisterInfo(RecordKeeper &RK, raw_ostream &OS) { in EmitRegisterInfo() argument
1503 RegisterInfoEmitter(RK).run(OS); in EmitRegisterInfo()