61   void EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
63   void emitComposeSubRegIndices(raw_ostream &OS, CodeGenRegBank &RegBank,
65   void emitComposeSubRegIndexLaneMask(raw_ostream &OS, CodeGenRegBank &RegBank,
173 EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,  in EmitRegUnitPressure()  argument
175   unsigned NumRCs = RegBank.getRegClasses().size();  in EmitRegUnitPressure()
176   unsigned NumSets = RegBank.getNumRegPressureSets();  in EmitRegUnitPressure()
182   for (const auto &RC : RegBank.getRegClasses()) {  in EmitRegUnitPressure()
189       OS << "    {" << (*Regs.begin())->getWeight(RegBank)  in EmitRegUnitPressure()
190          << ", " << RegBank.getRegUnitSetWeight(RegUnits);  in EmitRegUnitPressure()
201   for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits();  in EmitRegUnitPressure()
203     if (RegBank.getRegUnit(UnitIdx).Weight > 1)  in EmitRegUnitPressure()
209      << "  assert(RegUnit < " << RegBank.getNumNativeRegUnits()  in EmitRegUnitPressure()
213     for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits();  in EmitRegUnitPressure()
215       const RegUnit &RU = RegBank.getRegUnit(UnitIdx);  in EmitRegUnitPressure()
239     const RegUnitSet &RegUnits = RegBank.getRegSetAt(i);  in EmitRegUnitPressure()
254     const RegUnitSet &RegUnits = RegBank.getRegSetAt(i);  in EmitRegUnitPressure()
266   unsigned NumRCUnitSets = RegBank.getNumRegClassPressureSetLists();  in EmitRegUnitPressure()
270     ArrayRef<unsigned> PSetIDs = RegBank.getRCPressureSetIDs(i);  in EmitRegUnitPressure()
274       PSets[i].push_back(RegBank.getRegPressureSet(*PSetI).Order);  in EmitRegUnitPressure()
306      << "  assert(RegUnit < " << RegBank.getNumNativeRegUnits()  in EmitRegUnitPressure()
310   for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits();  in EmitRegUnitPressure()
312     OS << PSetsSeqs.get(PSets[RegBank.getRegUnit(UnitIdx).RegClassUnitSetsIdx])  in EmitRegUnitPressure()
631                                               CodeGenRegBank &RegBank,  in emitComposeSubRegIndices()  argument
633   const auto &SubRegIndices = RegBank.getSubRegIndices();  in emitComposeSubRegIndices()
701                                                     CodeGenRegBank &RegBank,  in emitComposeSubRegIndexLaneMask()  argument
704   const auto &SubRegIndices = RegBank.getSubRegIndices();  in emitComposeSubRegIndexLaneMask()
784                                CodeGenRegBank &RegBank) {  in runMCDesc()  argument
790   const auto &Regs = RegBank.getRegisters();  in runMCDesc()
792   auto &SubRegIndices = RegBank.getSubRegIndices();  in runMCDesc()
824     Reg.addSubRegsPreOrder(SR, RegBank);  in runMCDesc()
938   for (unsigned i = 0, e = RegBank.getNumNativeRegUnits(); i != e; ++i) {  in runMCDesc()
939     ArrayRef<const CodeGenRegister*> Roots = RegBank.getRegUnit(i).getRoots();  in runMCDesc()
949   const auto &RegisterClasses = RegBank.getRegClasses();  in runMCDesc()
1043      << RegBank.getNumNativeRegUnits() << ", " << TargetName << "RegDiffLists, "  in runMCDesc()
1060                                      CodeGenRegBank &RegBank) {  in runTargetHeader()  argument
1078   if (!RegBank.getSubRegIndices().empty()) {  in runTargetHeader()
1104   const auto &RegisterClasses = RegBank.getRegClasses();  in runTargetHeader()
1127                                    CodeGenRegBank &RegBank){  in runTargetDesc()  argument
1140   const auto &RegisterClasses = RegBank.getRegClasses();  in runTargetDesc()
1141   const auto &SubRegIndices = RegBank.getSubRegIndices();  in runTargetDesc()
1325   const auto &Regs = RegBank.getRegisters();  in runTargetDesc()
1340     emitComposeSubRegIndices(OS, RegBank, ClassName);  in runTargetDesc()
1341     emitComposeSubRegIndexLaneMask(OS, RegBank, ClassName);  in runTargetDesc()
1376   EmitRegUnitPressure(OS, RegBank, ClassName);  in runTargetDesc()
1397   OS.write_hex(RegBank.CoveringLanes);  in runTargetDesc()
1403      << "                     " << RegBank.getNumNativeRegUnits() << ",\n"  in runTargetDesc()
1423     const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet);  in runTargetDesc()
1434     BitVector Covered = RegBank.computeCoveredRegisters(*Regs);  in runTargetDesc()
1441       RegBank.getSets().evaluate(OPDag, OPSet, CSRSet->getLoc());  in runTargetDesc()
1442       Covered |= RegBank.computeCoveredRegisters(  in runTargetDesc()
1491   CodeGenRegBank &RegBank = Target.getRegBank();  in run()  local
1492   RegBank.computeDerivedInfo();  in run()
1494   runEnums(OS, Target, RegBank);  in run()
1495   runMCDesc(OS, Target, RegBank);  in run()
1496   runTargetHeader(OS, Target, RegBank);  in run()
1497   runTargetDesc(OS, Target, RegBank);  in run()