86   void EmitProcessorResources(const CodeGenProcModel &ProcModel,
89                              const CodeGenProcModel &ProcModel);
91                           const CodeGenProcModel &ProcModel);
93                            const CodeGenProcModel &ProcModel);
94   void GenSchedClassTables(const CodeGenProcModel &ProcModel,
424     const CodeGenProcModel &ProcModel = *PI;  in EmitStageAndOperandCycleData()  local
432     if (!ProcModel.hasItineraries())  in EmitStageAndOperandCycleData()
435     const std::string &Name = ProcModel.ItinsDef->getName();  in EmitStageAndOperandCycleData()
438     assert(ProcModel.ItinDefList.size() == ItinList.size() && "bad Itins");  in EmitStageAndOperandCycleData()
444       Record *ItinData = ProcModel.ItinDefList[SchedClassIdx];  in EmitStageAndOperandCycleData()
605 void SubtargetEmitter::EmitProcessorResources(const CodeGenProcModel &ProcModel,  in EmitProcessorResources()  argument
607   char Sep = ProcModel.ProcResourceDefs.empty() ? ' ' : ',';  in EmitProcessorResources()
611      << ProcModel.ModelName << "ProcResources" << "[] = {\n"  in EmitProcessorResources()
614   for (unsigned i = 0, e = ProcModel.ProcResourceDefs.size(); i < e; ++i) {  in EmitProcessorResources()
615     Record *PRDef = ProcModel.ProcResourceDefs[i];  in EmitProcessorResources()
632           PRDef->getValueAsDef("Super"), ProcModel);  in EmitProcessorResources()
633         SuperIdx = ProcModel.getProcResourceIdx(SuperDef);  in EmitProcessorResources()
655   const CodeGenSchedRW &SchedWrite, const CodeGenProcModel &ProcModel) {  in FindWriteResources()  argument
669       if (&SchedModels.getProcModel(ModelDef) != &ProcModel)  in FindWriteResources()
674                     "defined for processor " + ProcModel.ModelName +  in FindWriteResources()
683   for (RecIter WRI = ProcModel.WriteResDefs.begin(),  in FindWriteResources()
684          WRE = ProcModel.WriteResDefs.end(); WRI != WRE; ++WRI) {  in FindWriteResources()
692                       ProcModel.ModelName);  in FindWriteResources()
700     PrintFatalError(ProcModel.ModelDef->getLoc(),  in FindWriteResources()
710                                           const CodeGenProcModel &ProcModel) {  in FindReadAdvance()  argument
723       if (&SchedModels.getProcModel(ModelDef) != &ProcModel)  in FindReadAdvance()
728                     "defined for processor " + ProcModel.ModelName +  in FindReadAdvance()
737   for (RecIter RAI = ProcModel.ReadAdvanceDefs.begin(),  in FindReadAdvance()
738          RAE = ProcModel.ReadAdvanceDefs.end(); RAI != RAE; ++RAI) {  in FindReadAdvance()
746                       ProcModel.ModelName);  in FindReadAdvance()
754     PrintFatalError(ProcModel.ModelDef->getLoc(),  in FindReadAdvance()
813 void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel,  in GenSchedClassTables()  argument
816   if (!ProcModel.hasInstrSchedModel())  in GenSchedClassTables()
844                                 TI->ProcIndices.end(), ProcModel.Index);  in GenSchedClassTables()
861                                 SCI->ProcIndices.end(), ProcModel.Index);  in GenSchedClassTables()
874         if (&ProcModel == &SchedModels.getProcModel(RWModelDef)) {  in GenSchedClassTables()
888       for (RecIter II = ProcModel.ItinRWDefs.begin(),  in GenSchedClassTables()
889              IE = ProcModel.ItinRWDefs.end(); II != IE; ++II) {  in GenSchedClassTables()
899         DEBUG(dbgs() << ProcModel.ModelName  in GenSchedClassTables()
911                                      ProcModel);  in GenSchedClassTables()
930           FindWriteResources(SchedModels.getSchedWrite(*WSI), ProcModel);  in GenSchedClassTables()
947         ExpandProcResources(PRVec, Cycles, ProcModel);  in GenSchedClassTables()
952           WPREntry.ProcResourceIdx = ProcModel.getProcResourceIdx(PRVec[PRIdx]);  in GenSchedClassTables()
978         FindReadAdvance(SchedModels.getSchedRead(Reads[UseIdx]), ProcModel);  in GenSchedClassTables()