117 emit_src(struct nv30_context *nv30, struct nvfx_vpc *vpc, uint32_t *hw,  in emit_src()  argument
133       hw[1] |= (src.reg.index << NVFX_VP(INST_INPUT_SRC_SHIFT));  in emit_src()
143          hw[1] |= (src.reg.index << NVFX_VP(INST_CONST_SRC_SHIFT)) &  in emit_src()
159       hw[0] |= (1 << (21 + pos));  in emit_src()
168          hw[3] |= NVFX_VP(INST_INDEX_CONST);  in emit_src()
170          hw[0] |= NVFX_VP(INST_INDEX_INPUT);  in emit_src()
175          hw[0] |= NVFX_VP(INST_ADDR_REG_SELECT_1);  in emit_src()
176       hw[0] |= src.indirect_swz << NVFX_VP(INST_ADDR_SWZ_SHIFT);  in emit_src()
181       hw[1] |= ((sr & NVFX_VP(SRC0_HIGH_MASK)) >>  in emit_src()
183       hw[2] |= (sr & NVFX_VP(SRC0_LOW_MASK)) <<  in emit_src()
187       hw[2] |= sr << NVFX_VP(INST_SRC1_SHIFT);  in emit_src()
190       hw[2] |= ((sr & NVFX_VP(SRC2_HIGH_MASK)) >>  in emit_src()
192       hw[3] |= (sr & NVFX_VP(SRC2_LOW_MASK)) <<  in emit_src()
201 emit_dst(struct nv30_context *nv30, struct nvfx_vpc *vpc, uint32_t *hw,  in emit_dst()  argument
209          hw[0] |= NV30_VP_INST_DEST_TEMP_ID_MASK;  in emit_dst()
211          hw[3] |= NV40_VP_INST_DEST_MASK;  in emit_dst()
213             hw[0] |= NV40_VP_INST_VEC_DEST_TEMP_MASK;  in emit_dst()
215             hw[3] |= NV40_VP_INST_SCA_DEST_TEMP_MASK;  in emit_dst()
220          hw[0] |= (dst.index << NV30_VP_INST_DEST_TEMP_ID_SHIFT);  in emit_dst()
222          hw[3] |= NV40_VP_INST_DEST_MASK;  in emit_dst()
224             hw[0] |= (dst.index << NV40_VP_INST_VEC_DEST_TEMP_SHIFT);  in emit_dst()
226             hw[3] |= (dst.index << NV40_VP_INST_SCA_DEST_TEMP_SHIFT);  in emit_dst()
267          hw[3] |= (dst.index << NV30_VP_INST_DEST_SHIFT);  in emit_dst()
268          hw[0] |= NV30_VP_INST_VEC_DEST_TEMP_MASK;  in emit_dst()
273          hw[3] |= 0x800;  in emit_dst()
275          hw[3] |= (dst.index << NV40_VP_INST_DEST_SHIFT);  in emit_dst()
277             hw[0] |= NV40_VP_INST_VEC_RESULT;  in emit_dst()
278             hw[0] |= NV40_VP_INST_VEC_DEST_TEMP_MASK;  in emit_dst()
280             hw[3] |= NV40_VP_INST_SCA_RESULT;  in emit_dst()
281             hw[3] |= NV40_VP_INST_SCA_DEST_TEMP_MASK;  in emit_dst()
297    uint32_t *hw;  in nvfx_vp_emit()  local
303    hw = vpc->vpi->data;  in nvfx_vp_emit()
306       hw[0] |= NVFX_VP(INST_COND_TEST_ENABLE);  in nvfx_vp_emit()
307    hw[0] |= (insn.cc_test << NVFX_VP(INST_COND_SHIFT));  in nvfx_vp_emit()
308    hw[0] |= ((insn.cc_swz[0] << NVFX_VP(INST_COND_SWZ_X_SHIFT)) |  in nvfx_vp_emit()
313       hw[0] |= NVFX_VP(INST_COND_UPDATE_ENABLE);  in nvfx_vp_emit()
318          hw[0] |= NV40_VP_INST_SATURATE;  in nvfx_vp_emit()
323          hw[1] |= (op << NV30_VP_INST_VEC_OPCODE_SHIFT);  in nvfx_vp_emit()
325          hw[0] |= ((op >> 4) << NV30_VP_INST_SCA_OPCODEH_SHIFT);  in nvfx_vp_emit()
326          hw[1] |= ((op & 0xf) << NV30_VP_INST_SCA_OPCODEL_SHIFT);  in nvfx_vp_emit()
333             hw[3] |= (insn.mask << NV30_VP_INST_SDEST_WRITEMASK_SHIFT);  in nvfx_vp_emit()
335             hw[3] |= (insn.mask << NV30_VP_INST_VDEST_WRITEMASK_SHIFT);  in nvfx_vp_emit()
338             hw[3] |= (insn.mask << NV30_VP_INST_STEMP_WRITEMASK_SHIFT);  in nvfx_vp_emit()
340             hw[3] |= (insn.mask << NV30_VP_INST_VTEMP_WRITEMASK_SHIFT);  in nvfx_vp_emit()
344          hw[1] |= (op << NV40_VP_INST_VEC_OPCODE_SHIFT);  in nvfx_vp_emit()
345          hw[3] |= NV40_VP_INST_SCA_DEST_TEMP_MASK;  in nvfx_vp_emit()
346          hw[3] |= (insn.mask << NV40_VP_INST_VEC_WRITEMASK_SHIFT);  in nvfx_vp_emit()
348          hw[1] |= (op << NV40_VP_INST_SCA_OPCODE_SHIFT);  in nvfx_vp_emit()
349          hw[0] |= NV40_VP_INST_VEC_DEST_TEMP_MASK ;  in nvfx_vp_emit()
350          hw[3] |= (insn.mask << NV40_VP_INST_SCA_WRITEMASK_SHIFT);  in nvfx_vp_emit()
354    emit_dst(nv30, vpc, hw, slot, insn.dst);  in nvfx_vp_emit()
355    emit_src(nv30, vpc, hw, 0, insn.src[0]);  in nvfx_vp_emit()
356    emit_src(nv30, vpc, hw, 1, insn.src[1]);  in nvfx_vp_emit()
357    emit_src(nv30, vpc, hw, 2, insn.src[2]);  in nvfx_vp_emit()
822    int hw = 0, i;  in nvfx_vertprog_parse_decl_output()  local
826       hw = NVFX_VP(INST_DEST_POS);  in nvfx_vertprog_parse_decl_output()
836          hw = NVFX_VP(INST_DEST_COL0);  in nvfx_vertprog_parse_decl_output()
839          hw = NVFX_VP(INST_DEST_COL1);  in nvfx_vertprog_parse_decl_output()
847          hw = NVFX_VP(INST_DEST_BFC0);  in nvfx_vertprog_parse_decl_output()
850          hw = NVFX_VP(INST_DEST_BFC1);  in nvfx_vertprog_parse_decl_output()
857       hw = NVFX_VP(INST_DEST_FOGC);  in nvfx_vertprog_parse_decl_output()
860       hw = NVFX_VP(INST_DEST_PSZ);  in nvfx_vertprog_parse_decl_output()
865             hw = NVFX_VP(INST_DEST_TC(i));  in nvfx_vertprog_parse_decl_output()
884    vpc->r_result[idx] = nvfx_reg(NVFXSR_OUTPUT, hw);  in nvfx_vertprog_parse_decl_output()