Lines Matching refs:Inst

45   field bits<32> Inst;
51   field bits<64> Inst;
129   let Inst{3-0} = EN;
130   let Inst{9-4} = TGT;
131   let Inst{10} = COMPR;
132   let Inst{11} = DONE;
133   let Inst{12} = VM;
134   let Inst{31-26} = 0x3e;
135   let Inst{39-32} = VSRC0;
136   let Inst{47-40} = VSRC1;
137   let Inst{55-48} = VSRC2;
138   let Inst{63-56} = VSRC3;
161   let Inst{11-8} = DMASK;
162   let Inst{12} = UNORM;
163   let Inst{13} = GLC;
164   let Inst{14} = DA;
165   let Inst{15} = R128;
166   let Inst{16} = TFE;
167   let Inst{17} = LWE;
168   let Inst{24-18} = op;
169   let Inst{25} = SLC;
170   let Inst{31-26} = 0x3c;
171   let Inst{39-32} = VADDR;
172   let Inst{47-40} = VDATA;
173   let Inst{52-48} = SRSRC;
174   let Inst{57-53} = SSAMP;
199   let Inst{11-0} = OFFSET;
200   let Inst{12} = OFFEN;
201   let Inst{13} = IDXEN;
202   let Inst{14} = GLC;
203   let Inst{15} = ADDR64;
204   let Inst{18-16} = op;
205   let Inst{22-19} = DFMT;
206   let Inst{25-23} = NFMT;
207   let Inst{31-26} = 0x3a; //encoding
208   let Inst{39-32} = VADDR;
209   let Inst{47-40} = VDATA;
210   let Inst{52-48} = SRSRC;
211   let Inst{54} = SLC;
212   let Inst{55} = TFE;
213   let Inst{63-56} = SOFFSET;
237   let Inst{11-0} = OFFSET;
238   let Inst{12} = OFFEN;
239   let Inst{13} = IDXEN;
240   let Inst{14} = GLC;
241   let Inst{15} = ADDR64;
242   let Inst{16} = LDS;
243   let Inst{24-18} = op;
244   let Inst{31-26} = 0x38; //encoding
245   let Inst{39-32} = VADDR;
246   let Inst{47-40} = VDATA;
247   let Inst{52-48} = SRSRC;
248   let Inst{54} = SLC;
249   let Inst{55} = TFE;
250   let Inst{63-56} = SOFFSET;
267   let Inst{7-0} = OFFSET;
268   let Inst{8} = IMM;
269   let Inst{14-9} = SBASE;
270   let Inst{21-15} = SDST;
271   let Inst{26-22} = op;
272   let Inst{31-27} = 0x18; //encoding
285   let Inst{7-0} = SSRC0;
286   let Inst{15-8} = op;
287   let Inst{22-16} = SDST;
288   let Inst{31-23} = 0x17d; //encoding;
299   let Inst{7-0} = SSRC0;
300   let Inst{15-8} = SSRC1;
301   let Inst{22-16} = SDST;
302   let Inst{29-23} = op;
303   let Inst{31-30} = 0x2; // encoding
313   let Inst{7-0} = SSRC0;
314   let Inst{15-8} = SSRC1;
315   let Inst{22-16} = op;
316   let Inst{31-23} = 0x17e;
328   let Inst{15-0} = SIMM16;
329   let Inst{22-16} = SDST;
330   let Inst{27-23} = op;
331   let Inst{31-28} = 0xb; //encoding
343   let Inst{15-0} = SIMM16;
344   let Inst{22-16} = op;
345   let Inst{31-23} = 0x17f; // encoding
358   let Inst{7-0} = VSRC;
359   let Inst{9-8} = ATTRCHAN;
360   let Inst{15-10} = ATTR;
361   let Inst{17-16} = op;
362   let Inst{25-18} = VDST;
363   let Inst{31-26} = 0x32; // encoding
375   let Inst{8-0} = SRC0;
376   let Inst{16-9} = op;
377   let Inst{24-17} = VDST;
378   let Inst{31-25} = 0x3f; //encoding
391   let Inst{8-0} = SRC0;
392   let Inst{16-9} = VSRC1;
393   let Inst{24-17} = VDST;
394   let Inst{30-25} = op;
395   let Inst{31} = 0x0; //encoding
413   let Inst{7-0} = VDST;
414   let Inst{10-8} = ABS;
415   let Inst{11} = CLAMP;
416   let Inst{25-17} = op;
417   let Inst{31-26} = 0x34; //encoding
418   let Inst{40-32} = SRC0;
419   let Inst{49-41} = SRC1;
420   let Inst{58-50} = SRC2;
421   let Inst{60-59} = OMOD;
422   let Inst{63-61} = NEG;
434   let Inst{8-0} = SRC0;
435   let Inst{16-9} = VSRC1;
436   let Inst{24-17} = op;
437   let Inst{31-25} = 0x3e;