Lines Matching refs:V
14 #define TARGET_ARCH_OPCODE_LIST(V) \ argument
15 V(IA32Add) \
16 V(IA32And) \
17 V(IA32Cmp) \
18 V(IA32Test) \
19 V(IA32Or) \
20 V(IA32Xor) \
21 V(IA32Sub) \
22 V(IA32Imul) \
23 V(IA32ImulHigh) \
24 V(IA32UmulHigh) \
25 V(IA32Idiv) \
26 V(IA32Udiv) \
27 V(IA32Not) \
28 V(IA32Neg) \
29 V(IA32Shl) \
30 V(IA32Shr) \
31 V(IA32Sar) \
32 V(IA32Ror) \
33 V(IA32Lzcnt) \
34 V(IA32Tzcnt) \
35 V(IA32Popcnt) \
36 V(SSEFloat32Cmp) \
37 V(SSEFloat32Add) \
38 V(SSEFloat32Sub) \
39 V(SSEFloat32Mul) \
40 V(SSEFloat32Div) \
41 V(SSEFloat32Max) \
42 V(SSEFloat32Min) \
43 V(SSEFloat32Abs) \
44 V(SSEFloat32Neg) \
45 V(SSEFloat32Sqrt) \
46 V(SSEFloat32Round) \
47 V(SSEFloat64Cmp) \
48 V(SSEFloat64Add) \
49 V(SSEFloat64Sub) \
50 V(SSEFloat64Mul) \
51 V(SSEFloat64Div) \
52 V(SSEFloat64Mod) \
53 V(SSEFloat64Max) \
54 V(SSEFloat64Min) \
55 V(SSEFloat64Abs) \
56 V(SSEFloat64Neg) \
57 V(SSEFloat64Sqrt) \
58 V(SSEFloat64Round) \
59 V(SSEFloat32ToFloat64) \
60 V(SSEFloat64ToFloat32) \
61 V(SSEFloat64ToInt32) \
62 V(SSEFloat64ToUint32) \
63 V(SSEInt32ToFloat64) \
64 V(SSEUint32ToFloat64) \
65 V(SSEFloat64ExtractLowWord32) \
66 V(SSEFloat64ExtractHighWord32) \
67 V(SSEFloat64InsertLowWord32) \
68 V(SSEFloat64InsertHighWord32) \
69 V(SSEFloat64LoadLowWord32) \
70 V(AVXFloat32Add) \
71 V(AVXFloat32Sub) \
72 V(AVXFloat32Mul) \
73 V(AVXFloat32Div) \
74 V(AVXFloat32Max) \
75 V(AVXFloat32Min) \
76 V(AVXFloat64Add) \
77 V(AVXFloat64Sub) \
78 V(AVXFloat64Mul) \
79 V(AVXFloat64Div) \
80 V(AVXFloat64Max) \
81 V(AVXFloat64Min) \
82 V(AVXFloat64Abs) \
83 V(AVXFloat64Neg) \
84 V(AVXFloat32Abs) \
85 V(AVXFloat32Neg) \
86 V(IA32Movsxbl) \
87 V(IA32Movzxbl) \
88 V(IA32Movb) \
89 V(IA32Movsxwl) \
90 V(IA32Movzxwl) \
91 V(IA32Movw) \
92 V(IA32Movl) \
93 V(IA32Movss) \
94 V(IA32Movsd) \
95 V(IA32BitcastFI) \
96 V(IA32BitcastIF) \
97 V(IA32Lea) \
98 V(IA32Push) \
99 V(IA32PushFloat32) \
100 V(IA32PushFloat64) \
101 V(IA32Poke) \
102 V(IA32StackCheck)
117 #define TARGET_ADDRESSING_MODE_LIST(V) \ argument
118 V(MR) /* [%r1 ] */ \
119 V(MRI) /* [%r1 + K] */ \
120 V(MR1) /* [%r1 + %r2*1 ] */ \
121 V(MR2) /* [%r1 + %r2*2 ] */ \
122 V(MR4) /* [%r1 + %r2*4 ] */ \
123 V(MR8) /* [%r1 + %r2*8 ] */ \
124 V(MR1I) /* [%r1 + %r2*1 + K] */ \
125 V(MR2I) /* [%r1 + %r2*2 + K] */ \
126 V(MR4I) /* [%r1 + %r2*3 + K] */ \
127 V(MR8I) /* [%r1 + %r2*4 + K] */ \
128 V(M1) /* [ %r2*1 ] */ \
129 V(M2) /* [ %r2*2 ] */ \
130 V(M4) /* [ %r2*4 ] */ \
131 V(M8) /* [ %r2*8 ] */ \
132 V(M1I) /* [ %r2*1 + K] */ \
133 V(M2I) /* [ %r2*2 + K] */ \
134 V(M4I) /* [ %r2*4 + K] */ \
135 V(M8I) /* [ %r2*8 + K] */ \
136 V(MI) /* [ K] */