74   LOperand* destination = moves_[index].destination();  in PerformMove()  local
83     if (other_move.Blocks(destination) && !other_move.IsPending()) {  in PerformMove()
99   moves_[index].set_destination(destination);  in PerformMove()
103   if (moves_[index].source()->Equals(destination)) {  in PerformMove()
113     if (other_move.Blocks(destination)) {  in PerformMove()
129     LOperand* destination = moves_[i].destination();  in Verify()  local
131       SLOW_DCHECK(!destination->Equals(moves_[j].destination()));  in Verify()
143   LOperand* destination = moves_[index].destination();  in EmitMove()  local
149     if (destination->IsRegister()) {  in EmitMove()
150       Register dst = cgen_->ToRegister(destination);  in EmitMove()
153       DCHECK(destination->IsStackSlot());  in EmitMove()
154       Operand dst = cgen_->ToOperand(destination);  in EmitMove()
160     if (destination->IsRegister()) {  in EmitMove()
161       Register dst = cgen_->ToRegister(destination);  in EmitMove()
164       DCHECK(destination->IsStackSlot());  in EmitMove()
165       Operand dst = cgen_->ToOperand(destination);  in EmitMove()
172     if (destination->IsRegister()) {  in EmitMove()
173       Register dst = cgen_->ToRegister(destination);  in EmitMove()
188     } else if (destination->IsDoubleRegister()) {  in EmitMove()
191       XMMRegister dst = cgen_->ToDoubleRegister(destination);  in EmitMove()
199       DCHECK(destination->IsStackSlot());  in EmitMove()
200       Operand dst = cgen_->ToOperand(destination);  in EmitMove()
214     if (destination->IsDoubleRegister()) {  in EmitMove()
215       __ Movapd(cgen_->ToDoubleRegister(destination), src);  in EmitMove()
217       DCHECK(destination->IsDoubleStackSlot());  in EmitMove()
218       __ Movsd(cgen_->ToOperand(destination), src);  in EmitMove()
222     if (destination->IsDoubleRegister()) {  in EmitMove()
223       __ Movsd(cgen_->ToDoubleRegister(destination), src);  in EmitMove()
225       DCHECK(destination->IsDoubleStackSlot());  in EmitMove()
227       __ Movsd(cgen_->ToOperand(destination), xmm0);  in EmitMove()
239   LOperand* destination = moves_[index].destination();  in EmitSwap()  local
243   if (source->IsRegister() && destination->IsRegister()) {  in EmitSwap()
246     Register dst = cgen_->ToRegister(destination);  in EmitSwap()
251   } else if ((source->IsRegister() && destination->IsStackSlot()) ||  in EmitSwap()
252              (source->IsStackSlot() && destination->IsRegister())) {  in EmitSwap()
255         cgen_->ToRegister(source->IsRegister() ? source : destination);  in EmitSwap()
257         cgen_->ToOperand(source->IsRegister() ? destination : source);  in EmitSwap()
262   } else if ((source->IsStackSlot() && destination->IsStackSlot()) ||  in EmitSwap()
263       (source->IsDoubleStackSlot() && destination->IsDoubleStackSlot())) {  in EmitSwap()
266     Operand dst = cgen_->ToOperand(destination);  in EmitSwap()
272   } else if (source->IsDoubleRegister() && destination->IsDoubleRegister()) {  in EmitSwap()
275     XMMRegister destination_reg = cgen_->ToDoubleRegister(destination);  in EmitSwap()
280   } else if (source->IsDoubleRegister() || destination->IsDoubleRegister()) {  in EmitSwap()
282     DCHECK((source->IsDoubleRegister() && destination->IsDoubleStackSlot()) ||  in EmitSwap()
283            (source->IsDoubleStackSlot() && destination->IsDoubleRegister()));  in EmitSwap()
286                                                   : destination);  in EmitSwap()
287     LOperand* other = source->IsDoubleRegister() ? destination : source;  in EmitSwap()
309       moves_[i].set_source(destination);  in EmitSwap()
310     } else if (other_move.Blocks(destination)) {  in EmitSwap()