Lines Matching refs:rs
330 Register rs; in GetRsReg() local
331 rs.reg_code = (instr & kRsFieldMask) >> kRsShift; in GetRsReg()
332 return rs; in GetRsReg()
530 uint32_t rs = GetRsField(instr); in IsBeqc() local
532 return opcode == POP10 && rs != 0 && rs < rt; // && rt != 0 in IsBeqc()
538 uint32_t rs = GetRsField(instr); in IsBnec() local
540 return opcode == POP30 && rs != 0 && rs < rt; // && rt != 0 in IsBnec()
951 Register rs, in GenInstrRegister() argument
956 DCHECK(rd.is_valid() && rs.is_valid() && rt.is_valid() && is_uint5(sa)); in GenInstrRegister()
957 Instr instr = opcode | (rs.code() << kRsShift) | (rt.code() << kRtShift) in GenInstrRegister()
964 Register rs, in GenInstrRegister() argument
969 DCHECK(rs.is_valid() && rt.is_valid() && is_uint5(msb) && is_uint5(lsb)); in GenInstrRegister()
970 Instr instr = opcode | (rs.code() << kRsShift) | (rt.code() << kRtShift) in GenInstrRegister()
1029 void Assembler::GenInstrImmediate(Opcode opcode, Register rs, Register rt, in GenInstrImmediate() argument
1032 DCHECK(rs.is_valid() && rt.is_valid() && (is_int16(j) || is_uint16(j))); in GenInstrImmediate()
1033 Instr instr = opcode | (rs.code() << kRsShift) | (rt.code() << kRtShift) in GenInstrImmediate()
1039 void Assembler::GenInstrImmediate(Opcode opcode, Register rs, SecondaryField SF, in GenInstrImmediate() argument
1042 DCHECK(rs.is_valid() && (is_int16(j) || is_uint16(j))); in GenInstrImmediate()
1043 Instr instr = opcode | (rs.code() << kRsShift) | SF | (j & kImm16Mask); in GenInstrImmediate()
1048 void Assembler::GenInstrImmediate(Opcode opcode, Register rs, FPURegister ft, in GenInstrImmediate() argument
1051 DCHECK(rs.is_valid() && ft.is_valid() && (is_int16(j) || is_uint16(j))); in GenInstrImmediate()
1052 Instr instr = opcode | (rs.code() << kRsShift) | (ft.code() << kFtShift) in GenInstrImmediate()
1058 void Assembler::GenInstrImmediate(Opcode opcode, Register rs, int32_t offset21, in GenInstrImmediate() argument
1060 DCHECK(rs.is_valid() && (is_int21(offset21))); in GenInstrImmediate()
1061 Instr instr = opcode | (rs.code() << kRsShift) | (offset21 & kImm21Mask); in GenInstrImmediate()
1066 void Assembler::GenInstrImmediate(Opcode opcode, Register rs, in GenInstrImmediate() argument
1068 DCHECK(rs.is_valid() && (is_uint21(offset21))); in GenInstrImmediate()
1069 Instr instr = opcode | (rs.code() << kRsShift) | (offset21 & kImm21Mask); in GenInstrImmediate()
1211 void Assembler::beq(Register rs, Register rt, int16_t offset) { in beq() argument
1213 GenInstrImmediate(BEQ, rs, rt, offset); in beq()
1218 void Assembler::bgez(Register rs, int16_t offset) { in bgez() argument
1220 GenInstrImmediate(REGIMM, rs, BGEZ, offset); in bgez()
1232 void Assembler::bgeuc(Register rs, Register rt, int16_t offset) { in bgeuc() argument
1234 DCHECK(!(rs.is(zero_reg))); in bgeuc()
1236 DCHECK(rs.code() != rt.code()); in bgeuc()
1237 GenInstrImmediate(BLEZ, rs, rt, offset, CompactBranchType::COMPACT_BRANCH); in bgeuc()
1241 void Assembler::bgec(Register rs, Register rt, int16_t offset) { in bgec() argument
1243 DCHECK(!(rs.is(zero_reg))); in bgec()
1245 DCHECK(rs.code() != rt.code()); in bgec()
1246 GenInstrImmediate(BLEZL, rs, rt, offset, CompactBranchType::COMPACT_BRANCH); in bgec()
1250 void Assembler::bgezal(Register rs, int16_t offset) { in bgezal() argument
1251 DCHECK(!IsMipsArchVariant(kMips32r6) || rs.is(zero_reg)); in bgezal()
1254 GenInstrImmediate(REGIMM, rs, BGEZAL, offset); in bgezal()
1259 void Assembler::bgtz(Register rs, int16_t offset) { in bgtz() argument
1261 GenInstrImmediate(BGTZ, rs, zero_reg, offset); in bgtz()
1274 void Assembler::blez(Register rs, int16_t offset) { in blez() argument
1276 GenInstrImmediate(BLEZ, rs, zero_reg, offset); in blez()
1296 void Assembler::bltuc(Register rs, Register rt, int16_t offset) { in bltuc() argument
1298 DCHECK(!(rs.is(zero_reg))); in bltuc()
1300 DCHECK(rs.code() != rt.code()); in bltuc()
1301 GenInstrImmediate(BGTZ, rs, rt, offset, CompactBranchType::COMPACT_BRANCH); in bltuc()
1305 void Assembler::bltc(Register rs, Register rt, int16_t offset) { in bltc() argument
1307 DCHECK(!rs.is(zero_reg)); in bltc()
1309 DCHECK(rs.code() != rt.code()); in bltc()
1310 GenInstrImmediate(BGTZL, rs, rt, offset, CompactBranchType::COMPACT_BRANCH); in bltc()
1314 void Assembler::bltz(Register rs, int16_t offset) { in bltz() argument
1316 GenInstrImmediate(REGIMM, rs, BLTZ, offset); in bltz()
1321 void Assembler::bltzal(Register rs, int16_t offset) { in bltzal() argument
1322 DCHECK(!IsMipsArchVariant(kMips32r6) || rs.is(zero_reg)); in bltzal()
1325 GenInstrImmediate(REGIMM, rs, BLTZAL, offset); in bltzal()
1330 void Assembler::bne(Register rs, Register rt, int16_t offset) { in bne() argument
1332 GenInstrImmediate(BNE, rs, rt, offset); in bne()
1337 void Assembler::bovc(Register rs, Register rt, int16_t offset) { in bovc() argument
1339 DCHECK(!rs.is(zero_reg)); in bovc()
1340 if (rs.code() >= rt.code()) { in bovc()
1341 GenInstrImmediate(ADDI, rs, rt, offset, CompactBranchType::COMPACT_BRANCH); in bovc()
1343 GenInstrImmediate(ADDI, rt, rs, offset, CompactBranchType::COMPACT_BRANCH); in bovc()
1348 void Assembler::bnvc(Register rs, Register rt, int16_t offset) { in bnvc() argument
1350 DCHECK(!rs.is(zero_reg)); in bnvc()
1351 if (rs.code() >= rt.code()) { in bnvc()
1352 GenInstrImmediate(DADDI, rs, rt, offset, CompactBranchType::COMPACT_BRANCH); in bnvc()
1354 GenInstrImmediate(DADDI, rt, rs, offset, CompactBranchType::COMPACT_BRANCH); in bnvc()
1376 void Assembler::bgezall(Register rs, int16_t offset) { in bgezall() argument
1378 DCHECK(!(rs.is(zero_reg))); in bgezall()
1381 GenInstrImmediate(REGIMM, rs, BGEZALL, offset); in bgezall()
1421 void Assembler::beqc(Register rs, Register rt, int16_t offset) { in beqc() argument
1423 DCHECK(rs.code() != rt.code() && rs.code() != 0 && rt.code() != 0); in beqc()
1424 if (rs.code() < rt.code()) { in beqc()
1425 GenInstrImmediate(ADDI, rs, rt, offset, CompactBranchType::COMPACT_BRANCH); in beqc()
1427 GenInstrImmediate(ADDI, rt, rs, offset, CompactBranchType::COMPACT_BRANCH); in beqc()
1432 void Assembler::beqzc(Register rs, int32_t offset) { in beqzc() argument
1434 DCHECK(!(rs.is(zero_reg))); in beqzc()
1435 GenInstrImmediate(POP66, rs, offset, CompactBranchType::COMPACT_BRANCH); in beqzc()
1439 void Assembler::bnec(Register rs, Register rt, int16_t offset) { in bnec() argument
1441 DCHECK(rs.code() != rt.code() && rs.code() != 0 && rt.code() != 0); in bnec()
1442 if (rs.code() < rt.code()) { in bnec()
1443 GenInstrImmediate(DADDI, rs, rt, offset, CompactBranchType::COMPACT_BRANCH); in bnec()
1445 GenInstrImmediate(DADDI, rt, rs, offset, CompactBranchType::COMPACT_BRANCH); in bnec()
1450 void Assembler::bnezc(Register rs, int32_t offset) { in bnezc() argument
1452 DCHECK(!(rs.is(zero_reg))); in bnezc()
1453 GenInstrImmediate(POP76, rs, offset, CompactBranchType::COMPACT_BRANCH); in bnezc()
1471 void Assembler::jr(Register rs) { in jr() argument
1474 if (rs.is(ra)) { in jr()
1477 GenInstrRegister(SPECIAL, rs, zero_reg, zero_reg, 0, JR); in jr()
1480 jalr(rs, zero_reg); in jr()
1500 void Assembler::jalr(Register rs, Register rd) { in jalr() argument
1501 DCHECK(rs.code() != rd.code()); in jalr()
1504 GenInstrRegister(SPECIAL, rs, zero_reg, rd, 0, JALR); in jalr()
1526 void Assembler::addu(Register rd, Register rs, Register rt) { in addu() argument
1527 GenInstrRegister(SPECIAL, rs, rt, rd, 0, ADDU); in addu()
1531 void Assembler::addiu(Register rd, Register rs, int32_t j) { in addiu() argument
1532 GenInstrImmediate(ADDIU, rs, rd, j); in addiu()
1536 void Assembler::subu(Register rd, Register rs, Register rt) { in subu() argument
1537 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SUBU); in subu()
1541 void Assembler::mul(Register rd, Register rs, Register rt) { in mul() argument
1543 GenInstrRegister(SPECIAL2, rs, rt, rd, 0, MUL); in mul()
1545 GenInstrRegister(SPECIAL, rs, rt, rd, MUL_OP, MUL_MUH); in mul()
1550 void Assembler::mulu(Register rd, Register rs, Register rt) { in mulu() argument
1552 GenInstrRegister(SPECIAL, rs, rt, rd, MUL_OP, MUL_MUH_U); in mulu()
1556 void Assembler::muh(Register rd, Register rs, Register rt) { in muh() argument
1558 GenInstrRegister(SPECIAL, rs, rt, rd, MUH_OP, MUL_MUH); in muh()
1562 void Assembler::muhu(Register rd, Register rs, Register rt) { in muhu() argument
1564 GenInstrRegister(SPECIAL, rs, rt, rd, MUH_OP, MUL_MUH_U); in muhu()
1568 void Assembler::mod(Register rd, Register rs, Register rt) { in mod() argument
1570 GenInstrRegister(SPECIAL, rs, rt, rd, MOD_OP, DIV_MOD); in mod()
1574 void Assembler::modu(Register rd, Register rs, Register rt) { in modu() argument
1576 GenInstrRegister(SPECIAL, rs, rt, rd, MOD_OP, DIV_MOD_U); in modu()
1580 void Assembler::mult(Register rs, Register rt) { in mult() argument
1581 GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, MULT); in mult()
1585 void Assembler::multu(Register rs, Register rt) { in multu() argument
1586 GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, MULTU); in multu()
1590 void Assembler::div(Register rs, Register rt) { in div() argument
1591 GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, DIV); in div()
1595 void Assembler::div(Register rd, Register rs, Register rt) { in div() argument
1597 GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, DIV_MOD); in div()
1601 void Assembler::divu(Register rs, Register rt) { in divu() argument
1602 GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, DIVU); in divu()
1606 void Assembler::divu(Register rd, Register rs, Register rt) { in divu() argument
1608 GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, DIV_MOD_U); in divu()
1614 void Assembler::and_(Register rd, Register rs, Register rt) { in and_() argument
1615 GenInstrRegister(SPECIAL, rs, rt, rd, 0, AND); in and_()
1619 void Assembler::andi(Register rt, Register rs, int32_t j) { in andi() argument
1621 GenInstrImmediate(ANDI, rs, rt, j); in andi()
1625 void Assembler::or_(Register rd, Register rs, Register rt) { in or_() argument
1626 GenInstrRegister(SPECIAL, rs, rt, rd, 0, OR); in or_()
1630 void Assembler::ori(Register rt, Register rs, int32_t j) { in ori() argument
1632 GenInstrImmediate(ORI, rs, rt, j); in ori()
1636 void Assembler::xor_(Register rd, Register rs, Register rt) { in xor_() argument
1637 GenInstrRegister(SPECIAL, rs, rt, rd, 0, XOR); in xor_()
1641 void Assembler::xori(Register rt, Register rs, int32_t j) { in xori() argument
1643 GenInstrImmediate(XORI, rs, rt, j); in xori()
1647 void Assembler::nor(Register rd, Register rs, Register rt) { in nor() argument
1648 GenInstrRegister(SPECIAL, rs, rt, rd, 0, NOR); in nor()
1666 void Assembler::sllv(Register rd, Register rt, Register rs) { in sllv() argument
1667 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SLLV); in sllv()
1676 void Assembler::srlv(Register rd, Register rt, Register rs) { in srlv() argument
1677 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SRLV); in srlv()
1686 void Assembler::srav(Register rd, Register rt, Register rs) { in srav() argument
1687 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SRAV); in srav()
1701 void Assembler::rotrv(Register rd, Register rt, Register rs) { in rotrv() argument
1703 DCHECK(rd.is_valid() && rt.is_valid() && rs.is_valid()); in rotrv()
1705 Instr instr = SPECIAL | (rs.code() << kRsShift) | (rt.code() << kRtShift) in rotrv()
1711 void Assembler::lsa(Register rd, Register rt, Register rs, uint8_t sa) { in lsa() argument
1712 DCHECK(rd.is_valid() && rt.is_valid() && rs.is_valid()); in lsa()
1715 Instr instr = SPECIAL | (rs.code() << kRsShift) | (rt.code() << kRtShift) | in lsa()
1732 void Assembler::lb(Register rd, const MemOperand& rs) { in lb() argument
1733 if (is_int16(rs.offset_)) { in lb()
1734 GenInstrImmediate(LB, rs.rm(), rd, rs.offset_); in lb()
1736 LoadRegPlusOffsetToAt(rs); in lb()
1742 void Assembler::lbu(Register rd, const MemOperand& rs) { in lbu() argument
1743 if (is_int16(rs.offset_)) { in lbu()
1744 GenInstrImmediate(LBU, rs.rm(), rd, rs.offset_); in lbu()
1746 LoadRegPlusOffsetToAt(rs); in lbu()
1752 void Assembler::lh(Register rd, const MemOperand& rs) { in lh() argument
1753 if (is_int16(rs.offset_)) { in lh()
1754 GenInstrImmediate(LH, rs.rm(), rd, rs.offset_); in lh()
1756 LoadRegPlusOffsetToAt(rs); in lh()
1762 void Assembler::lhu(Register rd, const MemOperand& rs) { in lhu() argument
1763 if (is_int16(rs.offset_)) { in lhu()
1764 GenInstrImmediate(LHU, rs.rm(), rd, rs.offset_); in lhu()
1766 LoadRegPlusOffsetToAt(rs); in lhu()
1772 void Assembler::lw(Register rd, const MemOperand& rs) { in lw() argument
1773 if (is_int16(rs.offset_)) { in lw()
1774 GenInstrImmediate(LW, rs.rm(), rd, rs.offset_); in lw()
1776 LoadRegPlusOffsetToAt(rs); in lw()
1782 void Assembler::lwl(Register rd, const MemOperand& rs) { in lwl() argument
1783 GenInstrImmediate(LWL, rs.rm(), rd, rs.offset_); in lwl()
1787 void Assembler::lwr(Register rd, const MemOperand& rs) { in lwr() argument
1788 GenInstrImmediate(LWR, rs.rm(), rd, rs.offset_); in lwr()
1792 void Assembler::sb(Register rd, const MemOperand& rs) { in sb() argument
1793 if (is_int16(rs.offset_)) { in sb()
1794 GenInstrImmediate(SB, rs.rm(), rd, rs.offset_); in sb()
1796 LoadRegPlusOffsetToAt(rs); in sb()
1802 void Assembler::sh(Register rd, const MemOperand& rs) { in sh() argument
1803 if (is_int16(rs.offset_)) { in sh()
1804 GenInstrImmediate(SH, rs.rm(), rd, rs.offset_); in sh()
1806 LoadRegPlusOffsetToAt(rs); in sh()
1812 void Assembler::sw(Register rd, const MemOperand& rs) { in sw() argument
1813 if (is_int16(rs.offset_)) { in sw()
1814 GenInstrImmediate(SW, rs.rm(), rd, rs.offset_); in sw()
1816 LoadRegPlusOffsetToAt(rs); in sw()
1822 void Assembler::swl(Register rd, const MemOperand& rs) { in swl() argument
1823 GenInstrImmediate(SWL, rs.rm(), rd, rs.offset_); in swl()
1827 void Assembler::swr(Register rd, const MemOperand& rs) { in swr() argument
1828 GenInstrImmediate(SWR, rs.rm(), rd, rs.offset_); in swr()
1838 void Assembler::aui(Register rt, Register rs, int32_t j) { in aui() argument
1841 DCHECK(!(rs.is(zero_reg))); in aui()
1843 GenInstrImmediate(LUI, rs, rt, j); in aui()
1849 void Assembler::addiupc(Register rs, int32_t imm19) { in addiupc() argument
1851 DCHECK(rs.is_valid() && is_int19(imm19)); in addiupc()
1853 GenInstrImmediate(PCREL, rs, imm21); in addiupc()
1857 void Assembler::lwpc(Register rs, int32_t offset19) { in lwpc() argument
1859 DCHECK(rs.is_valid() && is_int19(offset19)); in lwpc()
1861 GenInstrImmediate(PCREL, rs, imm21); in lwpc()
1865 void Assembler::auipc(Register rs, int16_t imm16) { in auipc() argument
1867 DCHECK(rs.is_valid()); in auipc()
1869 GenInstrImmediate(PCREL, rs, imm21); in auipc()
1873 void Assembler::aluipc(Register rs, int16_t imm16) { in aluipc() argument
1875 DCHECK(rs.is_valid()); in aluipc()
1877 GenInstrImmediate(PCREL, rs, imm21); in aluipc()
1915 void Assembler::tge(Register rs, Register rt, uint16_t code) { in tge() argument
1917 Instr instr = SPECIAL | TGE | rs.code() << kRsShift in tge()
1923 void Assembler::tgeu(Register rs, Register rt, uint16_t code) { in tgeu() argument
1925 Instr instr = SPECIAL | TGEU | rs.code() << kRsShift in tgeu()
1931 void Assembler::tlt(Register rs, Register rt, uint16_t code) { in tlt() argument
1934 SPECIAL | TLT | rs.code() << kRsShift | rt.code() << kRtShift | code << 6; in tlt()
1939 void Assembler::tltu(Register rs, Register rt, uint16_t code) { in tltu() argument
1942 SPECIAL | TLTU | rs.code() << kRsShift in tltu()
1948 void Assembler::teq(Register rs, Register rt, uint16_t code) { in teq() argument
1951 SPECIAL | TEQ | rs.code() << kRsShift | rt.code() << kRtShift | code << 6; in teq()
1956 void Assembler::tne(Register rs, Register rt, uint16_t code) { in tne() argument
1959 SPECIAL | TNE | rs.code() << kRsShift | rt.code() << kRtShift | code << 6; in tne()
1977 void Assembler::slt(Register rd, Register rs, Register rt) { in slt() argument
1978 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SLT); in slt()
1982 void Assembler::sltu(Register rd, Register rs, Register rt) { in sltu() argument
1983 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SLTU); in sltu()
1987 void Assembler::slti(Register rt, Register rs, int32_t j) { in slti() argument
1988 GenInstrImmediate(SLTI, rs, rt, j); in slti()
1992 void Assembler::sltiu(Register rt, Register rs, int32_t j) { in sltiu() argument
1993 GenInstrImmediate(SLTIU, rs, rt, j); in sltiu()
1998 void Assembler::movz(Register rd, Register rs, Register rt) { in movz() argument
1999 GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVZ); in movz()
2003 void Assembler::movn(Register rd, Register rs, Register rt) { in movn() argument
2004 GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVN); in movn()
2008 void Assembler::movt(Register rd, Register rs, uint16_t cc) { in movt() argument
2011 GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVCI); in movt()
2015 void Assembler::movf(Register rd, Register rs, uint16_t cc) { in movf() argument
2018 GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVCI); in movf()
2022 void Assembler::seleqz(Register rd, Register rs, Register rt) { in seleqz() argument
2024 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SELEQZ_S); in seleqz()
2029 void Assembler::clz(Register rd, Register rs) { in clz() argument
2032 GenInstrRegister(SPECIAL2, rs, rd, rd, 0, CLZ); in clz()
2034 GenInstrRegister(SPECIAL, rs, zero_reg, rd, 1, CLZ_R6); in clz()
2039 void Assembler::ins_(Register rt, Register rs, uint16_t pos, uint16_t size) { in ins_() argument
2043 GenInstrRegister(SPECIAL3, rs, rt, pos + size - 1, pos, INS); in ins_()
2047 void Assembler::ext_(Register rt, Register rs, uint16_t pos, uint16_t size) { in ext_() argument
2051 GenInstrRegister(SPECIAL3, rs, rt, size - 1, pos, EXT); in ext_()
2061 void Assembler::pref(int32_t hint, const MemOperand& rs) { in pref() argument
2063 DCHECK(is_uint5(hint) && is_uint16(rs.offset_)); in pref()
2064 Instr instr = PREF | (rs.rm().code() << kRsShift) | (hint << kRtShift) in pref()
2065 | (rs.offset_); in pref()
2070 void Assembler::align(Register rd, Register rs, Register rt, uint8_t bp) { in align() argument
2074 GenInstrRegister(SPECIAL3, rs, rt, rd, sa, BSHFL); in align()
2252 void Assembler::selnez(Register rd, Register rs, Register rt) { in selnez() argument
2254 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SELNEZ_S); in selnez()