Lines Matching refs:rs
304 Register rs; in GetRsReg() local
305 rs.reg_code = (instr & kRsFieldMask) >> kRsShift; in GetRsReg()
306 return rs; in GetRsReg()
504 uint32_t rs = GetRsField(instr); in IsBeqc() local
506 return opcode == POP10 && rs != 0 && rs < rt; // && rt != 0 in IsBeqc()
512 uint32_t rs = GetRsField(instr); in IsBnec() local
514 return opcode == POP30 && rs != 0 && rs < rt; // && rt != 0 in IsBnec()
968 Register rs, in GenInstrRegister() argument
973 DCHECK(rd.is_valid() && rs.is_valid() && rt.is_valid() && is_uint5(sa)); in GenInstrRegister()
974 Instr instr = opcode | (rs.code() << kRsShift) | (rt.code() << kRtShift) in GenInstrRegister()
981 Register rs, in GenInstrRegister() argument
986 DCHECK(rs.is_valid() && rt.is_valid() && is_uint5(msb) && is_uint5(lsb)); in GenInstrRegister()
987 Instr instr = opcode | (rs.code() << kRsShift) | (rt.code() << kRtShift) in GenInstrRegister()
1046 void Assembler::GenInstrImmediate(Opcode opcode, Register rs, Register rt, in GenInstrImmediate() argument
1049 DCHECK(rs.is_valid() && rt.is_valid() && (is_int16(j) || is_uint16(j))); in GenInstrImmediate()
1050 Instr instr = opcode | (rs.code() << kRsShift) | (rt.code() << kRtShift) in GenInstrImmediate()
1056 void Assembler::GenInstrImmediate(Opcode opcode, Register rs, SecondaryField SF, in GenInstrImmediate() argument
1059 DCHECK(rs.is_valid() && (is_int16(j) || is_uint16(j))); in GenInstrImmediate()
1060 Instr instr = opcode | (rs.code() << kRsShift) | SF | (j & kImm16Mask); in GenInstrImmediate()
1065 void Assembler::GenInstrImmediate(Opcode opcode, Register rs, FPURegister ft, in GenInstrImmediate() argument
1068 DCHECK(rs.is_valid() && ft.is_valid() && (is_int16(j) || is_uint16(j))); in GenInstrImmediate()
1069 Instr instr = opcode | (rs.code() << kRsShift) | (ft.code() << kFtShift) in GenInstrImmediate()
1075 void Assembler::GenInstrImmediate(Opcode opcode, Register rs, int32_t offset21, in GenInstrImmediate() argument
1077 DCHECK(rs.is_valid() && (is_int21(offset21))); in GenInstrImmediate()
1078 Instr instr = opcode | (rs.code() << kRsShift) | (offset21 & kImm21Mask); in GenInstrImmediate()
1083 void Assembler::GenInstrImmediate(Opcode opcode, Register rs, in GenInstrImmediate() argument
1085 DCHECK(rs.is_valid() && (is_uint21(offset21))); in GenInstrImmediate()
1086 Instr instr = opcode | (rs.code() << kRsShift) | (offset21 & kImm21Mask); in GenInstrImmediate()
1247 void Assembler::beq(Register rs, Register rt, int16_t offset) { in beq() argument
1249 GenInstrImmediate(BEQ, rs, rt, offset); in beq()
1254 void Assembler::bgez(Register rs, int16_t offset) { in bgez() argument
1256 GenInstrImmediate(REGIMM, rs, BGEZ, offset); in bgez()
1268 void Assembler::bgeuc(Register rs, Register rt, int16_t offset) { in bgeuc() argument
1270 DCHECK(!(rs.is(zero_reg))); in bgeuc()
1272 DCHECK(rs.code() != rt.code()); in bgeuc()
1273 GenInstrImmediate(BLEZ, rs, rt, offset, CompactBranchType::COMPACT_BRANCH); in bgeuc()
1277 void Assembler::bgec(Register rs, Register rt, int16_t offset) { in bgec() argument
1279 DCHECK(!(rs.is(zero_reg))); in bgec()
1281 DCHECK(rs.code() != rt.code()); in bgec()
1282 GenInstrImmediate(BLEZL, rs, rt, offset, CompactBranchType::COMPACT_BRANCH); in bgec()
1286 void Assembler::bgezal(Register rs, int16_t offset) { in bgezal() argument
1287 DCHECK(kArchVariant != kMips64r6 || rs.is(zero_reg)); in bgezal()
1290 GenInstrImmediate(REGIMM, rs, BGEZAL, offset); in bgezal()
1295 void Assembler::bgtz(Register rs, int16_t offset) { in bgtz() argument
1297 GenInstrImmediate(BGTZ, rs, zero_reg, offset); in bgtz()
1310 void Assembler::blez(Register rs, int16_t offset) { in blez() argument
1312 GenInstrImmediate(BLEZ, rs, zero_reg, offset); in blez()
1332 void Assembler::bltuc(Register rs, Register rt, int16_t offset) { in bltuc() argument
1334 DCHECK(!(rs.is(zero_reg))); in bltuc()
1336 DCHECK(rs.code() != rt.code()); in bltuc()
1337 GenInstrImmediate(BGTZ, rs, rt, offset, CompactBranchType::COMPACT_BRANCH); in bltuc()
1341 void Assembler::bltc(Register rs, Register rt, int16_t offset) { in bltc() argument
1343 DCHECK(!rs.is(zero_reg)); in bltc()
1345 DCHECK(rs.code() != rt.code()); in bltc()
1346 GenInstrImmediate(BGTZL, rs, rt, offset, CompactBranchType::COMPACT_BRANCH); in bltc()
1350 void Assembler::bltz(Register rs, int16_t offset) { in bltz() argument
1352 GenInstrImmediate(REGIMM, rs, BLTZ, offset); in bltz()
1357 void Assembler::bltzal(Register rs, int16_t offset) { in bltzal() argument
1358 DCHECK(kArchVariant != kMips64r6 || rs.is(zero_reg)); in bltzal()
1361 GenInstrImmediate(REGIMM, rs, BLTZAL, offset); in bltzal()
1366 void Assembler::bne(Register rs, Register rt, int16_t offset) { in bne() argument
1368 GenInstrImmediate(BNE, rs, rt, offset); in bne()
1373 void Assembler::bovc(Register rs, Register rt, int16_t offset) { in bovc() argument
1375 DCHECK(!(rs.is(zero_reg))); in bovc()
1376 DCHECK(rs.code() >= rt.code()); in bovc()
1377 GenInstrImmediate(ADDI, rs, rt, offset, CompactBranchType::COMPACT_BRANCH); in bovc()
1381 void Assembler::bnvc(Register rs, Register rt, int16_t offset) { in bnvc() argument
1383 DCHECK(!(rs.is(zero_reg))); in bnvc()
1384 DCHECK(rs.code() >= rt.code()); in bnvc()
1385 GenInstrImmediate(DADDI, rs, rt, offset, CompactBranchType::COMPACT_BRANCH); in bnvc()
1406 void Assembler::bgezall(Register rs, int16_t offset) { in bgezall() argument
1408 DCHECK(!(rs.is(zero_reg))); in bgezall()
1411 GenInstrImmediate(REGIMM, rs, BGEZALL, offset); in bgezall()
1451 void Assembler::beqc(Register rs, Register rt, int16_t offset) { in beqc() argument
1453 DCHECK(rs.code() != rt.code() && rs.code() != 0 && rt.code() != 0); in beqc()
1454 if (rs.code() < rt.code()) { in beqc()
1455 GenInstrImmediate(ADDI, rs, rt, offset, CompactBranchType::COMPACT_BRANCH); in beqc()
1457 GenInstrImmediate(ADDI, rt, rs, offset, CompactBranchType::COMPACT_BRANCH); in beqc()
1462 void Assembler::beqzc(Register rs, int32_t offset) { in beqzc() argument
1464 DCHECK(!(rs.is(zero_reg))); in beqzc()
1465 GenInstrImmediate(POP66, rs, offset, CompactBranchType::COMPACT_BRANCH); in beqzc()
1469 void Assembler::bnec(Register rs, Register rt, int16_t offset) { in bnec() argument
1471 DCHECK(rs.code() != rt.code() && rs.code() != 0 && rt.code() != 0); in bnec()
1472 if (rs.code() < rt.code()) { in bnec()
1473 GenInstrImmediate(DADDI, rs, rt, offset, CompactBranchType::COMPACT_BRANCH); in bnec()
1475 GenInstrImmediate(DADDI, rt, rs, offset, CompactBranchType::COMPACT_BRANCH); in bnec()
1480 void Assembler::bnezc(Register rs, int32_t offset) { in bnezc() argument
1482 DCHECK(!(rs.is(zero_reg))); in bnezc()
1483 GenInstrImmediate(POP76, rs, offset, CompactBranchType::COMPACT_BRANCH); in bnezc()
1521 void Assembler::jr(Register rs) { in jr() argument
1524 if (rs.is(ra)) { in jr()
1527 GenInstrRegister(SPECIAL, rs, zero_reg, zero_reg, 0, JR); in jr()
1530 jalr(rs, zero_reg); in jr()
1543 void Assembler::jalr(Register rs, Register rd) { in jalr() argument
1544 DCHECK(rs.code() != rd.code()); in jalr()
1547 GenInstrRegister(SPECIAL, rs, zero_reg, rd, 0, JALR); in jalr()
1569 void Assembler::addu(Register rd, Register rs, Register rt) { in addu() argument
1570 GenInstrRegister(SPECIAL, rs, rt, rd, 0, ADDU); in addu()
1574 void Assembler::addiu(Register rd, Register rs, int32_t j) { in addiu() argument
1575 GenInstrImmediate(ADDIU, rs, rd, j); in addiu()
1579 void Assembler::subu(Register rd, Register rs, Register rt) { in subu() argument
1580 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SUBU); in subu()
1584 void Assembler::mul(Register rd, Register rs, Register rt) { in mul() argument
1586 GenInstrRegister(SPECIAL, rs, rt, rd, MUL_OP, MUL_MUH); in mul()
1588 GenInstrRegister(SPECIAL2, rs, rt, rd, 0, MUL); in mul()
1593 void Assembler::muh(Register rd, Register rs, Register rt) { in muh() argument
1595 GenInstrRegister(SPECIAL, rs, rt, rd, MUH_OP, MUL_MUH); in muh()
1599 void Assembler::mulu(Register rd, Register rs, Register rt) { in mulu() argument
1601 GenInstrRegister(SPECIAL, rs, rt, rd, MUL_OP, MUL_MUH_U); in mulu()
1605 void Assembler::muhu(Register rd, Register rs, Register rt) { in muhu() argument
1607 GenInstrRegister(SPECIAL, rs, rt, rd, MUH_OP, MUL_MUH_U); in muhu()
1611 void Assembler::dmul(Register rd, Register rs, Register rt) { in dmul() argument
1613 GenInstrRegister(SPECIAL, rs, rt, rd, MUL_OP, D_MUL_MUH); in dmul()
1617 void Assembler::dmuh(Register rd, Register rs, Register rt) { in dmuh() argument
1619 GenInstrRegister(SPECIAL, rs, rt, rd, MUH_OP, D_MUL_MUH); in dmuh()
1623 void Assembler::dmulu(Register rd, Register rs, Register rt) { in dmulu() argument
1625 GenInstrRegister(SPECIAL, rs, rt, rd, MUL_OP, D_MUL_MUH_U); in dmulu()
1629 void Assembler::dmuhu(Register rd, Register rs, Register rt) { in dmuhu() argument
1631 GenInstrRegister(SPECIAL, rs, rt, rd, MUH_OP, D_MUL_MUH_U); in dmuhu()
1635 void Assembler::mult(Register rs, Register rt) { in mult() argument
1637 GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, MULT); in mult()
1641 void Assembler::multu(Register rs, Register rt) { in multu() argument
1643 GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, MULTU); in multu()
1647 void Assembler::daddiu(Register rd, Register rs, int32_t j) { in daddiu() argument
1648 GenInstrImmediate(DADDIU, rs, rd, j); in daddiu()
1652 void Assembler::div(Register rs, Register rt) { in div() argument
1653 GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, DIV); in div()
1657 void Assembler::div(Register rd, Register rs, Register rt) { in div() argument
1659 GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, DIV_MOD); in div()
1663 void Assembler::mod(Register rd, Register rs, Register rt) { in mod() argument
1665 GenInstrRegister(SPECIAL, rs, rt, rd, MOD_OP, DIV_MOD); in mod()
1669 void Assembler::divu(Register rs, Register rt) { in divu() argument
1670 GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, DIVU); in divu()
1674 void Assembler::divu(Register rd, Register rs, Register rt) { in divu() argument
1676 GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, DIV_MOD_U); in divu()
1680 void Assembler::modu(Register rd, Register rs, Register rt) { in modu() argument
1682 GenInstrRegister(SPECIAL, rs, rt, rd, MOD_OP, DIV_MOD_U); in modu()
1686 void Assembler::daddu(Register rd, Register rs, Register rt) { in daddu() argument
1687 GenInstrRegister(SPECIAL, rs, rt, rd, 0, DADDU); in daddu()
1691 void Assembler::dsubu(Register rd, Register rs, Register rt) { in dsubu() argument
1692 GenInstrRegister(SPECIAL, rs, rt, rd, 0, DSUBU); in dsubu()
1696 void Assembler::dmult(Register rs, Register rt) { in dmult() argument
1697 GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, DMULT); in dmult()
1701 void Assembler::dmultu(Register rs, Register rt) { in dmultu() argument
1702 GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, DMULTU); in dmultu()
1706 void Assembler::ddiv(Register rs, Register rt) { in ddiv() argument
1707 GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, DDIV); in ddiv()
1711 void Assembler::ddiv(Register rd, Register rs, Register rt) { in ddiv() argument
1713 GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, D_DIV_MOD); in ddiv()
1717 void Assembler::dmod(Register rd, Register rs, Register rt) { in dmod() argument
1719 GenInstrRegister(SPECIAL, rs, rt, rd, MOD_OP, D_DIV_MOD); in dmod()
1723 void Assembler::ddivu(Register rs, Register rt) { in ddivu() argument
1724 GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, DDIVU); in ddivu()
1728 void Assembler::ddivu(Register rd, Register rs, Register rt) { in ddivu() argument
1730 GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, D_DIV_MOD_U); in ddivu()
1734 void Assembler::dmodu(Register rd, Register rs, Register rt) { in dmodu() argument
1736 GenInstrRegister(SPECIAL, rs, rt, rd, MOD_OP, D_DIV_MOD_U); in dmodu()
1742 void Assembler::and_(Register rd, Register rs, Register rt) { in and_() argument
1743 GenInstrRegister(SPECIAL, rs, rt, rd, 0, AND); in and_()
1747 void Assembler::andi(Register rt, Register rs, int32_t j) { in andi() argument
1749 GenInstrImmediate(ANDI, rs, rt, j); in andi()
1753 void Assembler::or_(Register rd, Register rs, Register rt) { in or_() argument
1754 GenInstrRegister(SPECIAL, rs, rt, rd, 0, OR); in or_()
1758 void Assembler::ori(Register rt, Register rs, int32_t j) { in ori() argument
1760 GenInstrImmediate(ORI, rs, rt, j); in ori()
1764 void Assembler::xor_(Register rd, Register rs, Register rt) { in xor_() argument
1765 GenInstrRegister(SPECIAL, rs, rt, rd, 0, XOR); in xor_()
1769 void Assembler::xori(Register rt, Register rs, int32_t j) { in xori() argument
1771 GenInstrImmediate(XORI, rs, rt, j); in xori()
1775 void Assembler::nor(Register rd, Register rs, Register rt) { in nor() argument
1776 GenInstrRegister(SPECIAL, rs, rt, rd, 0, NOR); in nor()
1794 void Assembler::sllv(Register rd, Register rt, Register rs) { in sllv() argument
1795 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SLLV); in sllv()
1804 void Assembler::srlv(Register rd, Register rt, Register rs) { in srlv() argument
1805 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SRLV); in srlv()
1814 void Assembler::srav(Register rd, Register rt, Register rs) { in srav() argument
1815 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SRAV); in srav()
1829 void Assembler::rotrv(Register rd, Register rt, Register rs) { in rotrv() argument
1831 DCHECK(rd.is_valid() && rt.is_valid() && rs.is_valid()); in rotrv()
1833 Instr instr = SPECIAL | (rs.code() << kRsShift) | (rt.code() << kRtShift) in rotrv()
1844 void Assembler::dsllv(Register rd, Register rt, Register rs) { in dsllv() argument
1845 GenInstrRegister(SPECIAL, rs, rt, rd, 0, DSLLV); in dsllv()
1854 void Assembler::dsrlv(Register rd, Register rt, Register rs) { in dsrlv() argument
1855 GenInstrRegister(SPECIAL, rs, rt, rd, 0, DSRLV); in dsrlv()
1867 void Assembler::drotrv(Register rd, Register rt, Register rs) { in drotrv() argument
1868 DCHECK(rd.is_valid() && rt.is_valid() && rs.is_valid() ); in drotrv()
1869 Instr instr = SPECIAL | (rs.code() << kRsShift) | (rt.code() << kRtShift) in drotrv()
1880 void Assembler::dsrav(Register rd, Register rt, Register rs) { in dsrav() argument
1881 GenInstrRegister(SPECIAL, rs, rt, rd, 0, DSRAV); in dsrav()
1900 void Assembler::lsa(Register rd, Register rt, Register rs, uint8_t sa) { in lsa() argument
1901 DCHECK(rd.is_valid() && rt.is_valid() && rs.is_valid()); in lsa()
1904 Instr instr = SPECIAL | (rs.code() << kRsShift) | (rt.code() << kRtShift) | in lsa()
1910 void Assembler::dlsa(Register rd, Register rt, Register rs, uint8_t sa) { in dlsa() argument
1911 DCHECK(rd.is_valid() && rt.is_valid() && rs.is_valid()); in dlsa()
1914 Instr instr = SPECIAL | (rs.code() << kRsShift) | (rt.code() << kRtShift) | in dlsa()
1933 void Assembler::lb(Register rd, const MemOperand& rs) { in lb() argument
1934 if (is_int16(rs.offset_)) { in lb()
1935 GenInstrImmediate(LB, rs.rm(), rd, rs.offset_); in lb()
1937 LoadRegPlusOffsetToAt(rs); in lb()
1943 void Assembler::lbu(Register rd, const MemOperand& rs) { in lbu() argument
1944 if (is_int16(rs.offset_)) { in lbu()
1945 GenInstrImmediate(LBU, rs.rm(), rd, rs.offset_); in lbu()
1947 LoadRegPlusOffsetToAt(rs); in lbu()
1953 void Assembler::lh(Register rd, const MemOperand& rs) { in lh() argument
1954 if (is_int16(rs.offset_)) { in lh()
1955 GenInstrImmediate(LH, rs.rm(), rd, rs.offset_); in lh()
1957 LoadRegPlusOffsetToAt(rs); in lh()
1963 void Assembler::lhu(Register rd, const MemOperand& rs) { in lhu() argument
1964 if (is_int16(rs.offset_)) { in lhu()
1965 GenInstrImmediate(LHU, rs.rm(), rd, rs.offset_); in lhu()
1967 LoadRegPlusOffsetToAt(rs); in lhu()
1973 void Assembler::lw(Register rd, const MemOperand& rs) { in lw() argument
1974 if (is_int16(rs.offset_)) { in lw()
1975 GenInstrImmediate(LW, rs.rm(), rd, rs.offset_); in lw()
1977 LoadRegPlusOffsetToAt(rs); in lw()
1983 void Assembler::lwu(Register rd, const MemOperand& rs) { in lwu() argument
1984 if (is_int16(rs.offset_)) { in lwu()
1985 GenInstrImmediate(LWU, rs.rm(), rd, rs.offset_); in lwu()
1987 LoadRegPlusOffsetToAt(rs); in lwu()
1993 void Assembler::lwl(Register rd, const MemOperand& rs) { in lwl() argument
1994 GenInstrImmediate(LWL, rs.rm(), rd, rs.offset_); in lwl()
1998 void Assembler::lwr(Register rd, const MemOperand& rs) { in lwr() argument
1999 GenInstrImmediate(LWR, rs.rm(), rd, rs.offset_); in lwr()
2003 void Assembler::sb(Register rd, const MemOperand& rs) { in sb() argument
2004 if (is_int16(rs.offset_)) { in sb()
2005 GenInstrImmediate(SB, rs.rm(), rd, rs.offset_); in sb()
2007 LoadRegPlusOffsetToAt(rs); in sb()
2013 void Assembler::sh(Register rd, const MemOperand& rs) { in sh() argument
2014 if (is_int16(rs.offset_)) { in sh()
2015 GenInstrImmediate(SH, rs.rm(), rd, rs.offset_); in sh()
2017 LoadRegPlusOffsetToAt(rs); in sh()
2023 void Assembler::sw(Register rd, const MemOperand& rs) { in sw() argument
2024 if (is_int16(rs.offset_)) { in sw()
2025 GenInstrImmediate(SW, rs.rm(), rd, rs.offset_); in sw()
2027 LoadRegPlusOffsetToAt(rs); in sw()
2033 void Assembler::swl(Register rd, const MemOperand& rs) { in swl() argument
2034 GenInstrImmediate(SWL, rs.rm(), rd, rs.offset_); in swl()
2038 void Assembler::swr(Register rd, const MemOperand& rs) { in swr() argument
2039 GenInstrImmediate(SWR, rs.rm(), rd, rs.offset_); in swr()
2049 void Assembler::aui(Register rt, Register rs, int32_t j) { in aui() argument
2053 GenInstrImmediate(LUI, rs, rt, j); in aui()
2057 void Assembler::daui(Register rt, Register rs, int32_t j) { in daui() argument
2059 DCHECK(!rs.is(zero_reg)); in daui()
2060 GenInstrImmediate(DAUI, rs, rt, j); in daui()
2064 void Assembler::dahi(Register rs, int32_t j) { in dahi() argument
2066 GenInstrImmediate(REGIMM, rs, DAHI, j); in dahi()
2070 void Assembler::dati(Register rs, int32_t j) { in dati() argument
2072 GenInstrImmediate(REGIMM, rs, DATI, j); in dati()
2076 void Assembler::ldl(Register rd, const MemOperand& rs) { in ldl() argument
2077 GenInstrImmediate(LDL, rs.rm(), rd, rs.offset_); in ldl()
2081 void Assembler::ldr(Register rd, const MemOperand& rs) { in ldr() argument
2082 GenInstrImmediate(LDR, rs.rm(), rd, rs.offset_); in ldr()
2086 void Assembler::sdl(Register rd, const MemOperand& rs) { in sdl() argument
2087 GenInstrImmediate(SDL, rs.rm(), rd, rs.offset_); in sdl()
2091 void Assembler::sdr(Register rd, const MemOperand& rs) { in sdr() argument
2092 GenInstrImmediate(SDR, rs.rm(), rd, rs.offset_); in sdr()
2096 void Assembler::ld(Register rd, const MemOperand& rs) { in ld() argument
2097 if (is_int16(rs.offset_)) { in ld()
2098 GenInstrImmediate(LD, rs.rm(), rd, rs.offset_); in ld()
2100 LoadRegPlusOffsetToAt(rs); in ld()
2106 void Assembler::sd(Register rd, const MemOperand& rs) { in sd() argument
2107 if (is_int16(rs.offset_)) { in sd()
2108 GenInstrImmediate(SD, rs.rm(), rd, rs.offset_); in sd()
2110 LoadRegPlusOffsetToAt(rs); in sd()
2118 void Assembler::addiupc(Register rs, int32_t imm19) { in addiupc() argument
2120 DCHECK(rs.is_valid() && is_int19(imm19)); in addiupc()
2122 GenInstrImmediate(PCREL, rs, imm21); in addiupc()
2126 void Assembler::lwpc(Register rs, int32_t offset19) { in lwpc() argument
2128 DCHECK(rs.is_valid() && is_int19(offset19)); in lwpc()
2130 GenInstrImmediate(PCREL, rs, imm21); in lwpc()
2134 void Assembler::lwupc(Register rs, int32_t offset19) { in lwupc() argument
2136 DCHECK(rs.is_valid() && is_int19(offset19)); in lwupc()
2138 GenInstrImmediate(PCREL, rs, imm21); in lwupc()
2142 void Assembler::ldpc(Register rs, int32_t offset18) { in ldpc() argument
2144 DCHECK(rs.is_valid() && is_int18(offset18)); in ldpc()
2146 GenInstrImmediate(PCREL, rs, imm21); in ldpc()
2150 void Assembler::auipc(Register rs, int16_t imm16) { in auipc() argument
2152 DCHECK(rs.is_valid()); in auipc()
2154 GenInstrImmediate(PCREL, rs, imm21); in auipc()
2158 void Assembler::aluipc(Register rs, int16_t imm16) { in aluipc() argument
2160 DCHECK(rs.is_valid()); in aluipc()
2162 GenInstrImmediate(PCREL, rs, imm21); in aluipc()
2200 void Assembler::tge(Register rs, Register rt, uint16_t code) { in tge() argument
2202 Instr instr = SPECIAL | TGE | rs.code() << kRsShift in tge()
2208 void Assembler::tgeu(Register rs, Register rt, uint16_t code) { in tgeu() argument
2210 Instr instr = SPECIAL | TGEU | rs.code() << kRsShift in tgeu()
2216 void Assembler::tlt(Register rs, Register rt, uint16_t code) { in tlt() argument
2219 SPECIAL | TLT | rs.code() << kRsShift | rt.code() << kRtShift | code << 6; in tlt()
2224 void Assembler::tltu(Register rs, Register rt, uint16_t code) { in tltu() argument
2227 SPECIAL | TLTU | rs.code() << kRsShift in tltu()
2233 void Assembler::teq(Register rs, Register rt, uint16_t code) { in teq() argument
2236 SPECIAL | TEQ | rs.code() << kRsShift | rt.code() << kRtShift | code << 6; in teq()
2241 void Assembler::tne(Register rs, Register rt, uint16_t code) { in tne() argument
2244 SPECIAL | TNE | rs.code() << kRsShift | rt.code() << kRtShift | code << 6; in tne()
2262 void Assembler::slt(Register rd, Register rs, Register rt) { in slt() argument
2263 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SLT); in slt()
2267 void Assembler::sltu(Register rd, Register rs, Register rt) { in sltu() argument
2268 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SLTU); in sltu()
2272 void Assembler::slti(Register rt, Register rs, int32_t j) { in slti() argument
2273 GenInstrImmediate(SLTI, rs, rt, j); in slti()
2277 void Assembler::sltiu(Register rt, Register rs, int32_t j) { in sltiu() argument
2278 GenInstrImmediate(SLTIU, rs, rt, j); in sltiu()
2283 void Assembler::movz(Register rd, Register rs, Register rt) { in movz() argument
2284 GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVZ); in movz()
2288 void Assembler::movn(Register rd, Register rs, Register rt) { in movn() argument
2289 GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVN); in movn()
2293 void Assembler::movt(Register rd, Register rs, uint16_t cc) { in movt() argument
2296 GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVCI); in movt()
2300 void Assembler::movf(Register rd, Register rs, uint16_t cc) { in movf() argument
2303 GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVCI); in movf()
2364 void Assembler::seleqz(Register rd, Register rs, Register rt) { in seleqz() argument
2366 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SELEQZ_S); in seleqz()
2371 void Assembler::selnez(Register rd, Register rs, Register rt) { in selnez() argument
2373 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SELNEZ_S); in selnez()
2378 void Assembler::clz(Register rd, Register rs) { in clz() argument
2381 GenInstrRegister(SPECIAL2, rs, rd, rd, 0, CLZ); in clz()
2383 GenInstrRegister(SPECIAL, rs, zero_reg, rd, 1, CLZ_R6); in clz()
2388 void Assembler::dclz(Register rd, Register rs) { in dclz() argument
2391 GenInstrRegister(SPECIAL2, rs, rd, rd, 0, DCLZ); in dclz()
2393 GenInstrRegister(SPECIAL, rs, zero_reg, rd, 1, DCLZ_R6); in dclz()
2398 void Assembler::ins_(Register rt, Register rs, uint16_t pos, uint16_t size) { in ins_() argument
2402 GenInstrRegister(SPECIAL3, rs, rt, pos + size - 1, pos, INS); in ins_()
2406 void Assembler::dins_(Register rt, Register rs, uint16_t pos, uint16_t size) { in dins_() argument
2410 GenInstrRegister(SPECIAL3, rs, rt, pos + size - 1, pos, DINS); in dins_()
2414 void Assembler::ext_(Register rt, Register rs, uint16_t pos, uint16_t size) { in ext_() argument
2418 GenInstrRegister(SPECIAL3, rs, rt, size - 1, pos, EXT); in ext_()
2422 void Assembler::dext_(Register rt, Register rs, uint16_t pos, uint16_t size) { in dext_() argument
2426 GenInstrRegister(SPECIAL3, rs, rt, size - 1, pos, DEXT); in dext_()
2430 void Assembler::dextm(Register rt, Register rs, uint16_t pos, uint16_t size) { in dextm() argument
2434 GenInstrRegister(SPECIAL3, rs, rt, size - 1 - 32, pos, DEXTM); in dextm()
2438 void Assembler::dextu(Register rt, Register rs, uint16_t pos, uint16_t size) { in dextu() argument
2442 GenInstrRegister(SPECIAL3, rs, rt, size - 1, pos - 32, DEXTU); in dextu()
2458 void Assembler::pref(int32_t hint, const MemOperand& rs) { in pref() argument
2459 DCHECK(is_uint5(hint) && is_uint16(rs.offset_)); in pref()
2460 Instr instr = PREF | (rs.rm().code() << kRsShift) | (hint << kRtShift) in pref()
2461 | (rs.offset_); in pref()
2466 void Assembler::align(Register rd, Register rs, Register rt, uint8_t bp) { in align() argument
2470 GenInstrRegister(SPECIAL3, rs, rt, rd, sa, BSHFL); in align()
2474 void Assembler::dalign(Register rd, Register rs, Register rt, uint8_t bp) { in dalign() argument
2478 GenInstrRegister(SPECIAL3, rs, rt, rd, sa, DBSHFL); in dalign()