Lines Matching refs:X01
229 #define X01 BITS2(0,1) macro
7529 case X01: in math_WIDEN_LO_OR_HI_LANES()
7570 case X01: amt = 16; break; in math_WIDEN_EVEN_OR_ODD_LANES()
7700 case X01: in math_VEC_DUP_IMM()
7918 vassert(size == X01 || size == X10); /* s or h only */ in math_SQDMULH()
7930 Int rcShift = size == X01 ? 15 : 31; in math_SQDMULH()
9107 if (bitU == 1 && sz <= X01 && opcode == BITS5(0,1,1,0,1)) { in dis_AdvSIMD_scalar_pairwise()
9110 Bool isD = sz == X01; in dis_AdvSIMD_scalar_pairwise()
9756 if (bitU == 0 && size <= X01 && opcode == BITS5(1,1,0,1,1)) { in dis_AdvSIMD_scalar_three_same()
9759 IRType ity = size == X01 ? Ity_F64 : Ity_F32; in dis_AdvSIMD_scalar_three_same()
9771 if (size <= X01 && opcode == BITS5(1,1,1,0,0)) { in dis_AdvSIMD_scalar_three_same()
9774 Bool isD = size == X01; in dis_AdvSIMD_scalar_three_same()
10039 if (opcode == BITS5(1,0,1,1,0) && bitU == 1 && size == X01) { in dis_AdvSIMD_scalar_two_reg_misc()
10104 if (size <= X01 && opcode == BITS5(1,1,1,0,1)) { in dis_AdvSIMD_scalar_two_reg_misc()
10269 case X01: in dis_AdvSIMD_scalar_x_indexed_element()
10312 case X01: in dis_AdvSIMD_scalar_x_indexed_element()
10333 HChar ch = size == X01 ? 'h' : 's'; in dis_AdvSIMD_scalar_x_indexed_element()
11652 if (size <= X01 && opcode == BITS5(1,1,0,1,1)) { in dis_AdvSIMD_three_same()
11670 if (size <= X01 && opcode == BITS5(1,1,1,0,0)) { in dis_AdvSIMD_three_same()
11752 if (bitU == 1 && size <= X01 && opcode == BITS5(1,1,0,1,0)) { in dis_AdvSIMD_three_same()
11754 Bool isD = size == X01; in dis_AdvSIMD_three_same()
11776 if (bitU == 1 && size <= X01 && opcode == BITS5(1,1,1,1,1)) { in dis_AdvSIMD_three_same()
11855 if (bitU == 1 && size <= X01 && opcode == BITS5(0,0,0,0,0)) { in dis_AdvSIMD_two_reg_misc()
11858 Bool isH = size == X01; in dis_AdvSIMD_two_reg_misc()
11972 if (bitU == 1 && size == X01 && opcode == BITS5(0,0,1,0,1)) { in dis_AdvSIMD_two_reg_misc()
12205 if (bitU == 0 && size <= X01 && opcode == BITS5(1,0,1,1,0)) { in dis_AdvSIMD_two_reg_misc()
12230 if (bitU == 1 && size == X01 && opcode == BITS5(1,0,1,1,0)) { in dis_AdvSIMD_two_reg_misc()
12255 if (bitU == 0 && size <= X01 && opcode == BITS5(1,0,1,1,1)) { in dis_AdvSIMD_two_reg_misc()
12414 if (size <= X01 && opcode == BITS5(1,1,1,0,1)) { in dis_AdvSIMD_two_reg_misc()
12592 case X01: in dis_AdvSIMD_vector_x_indexed_elem()
12605 HChar ch = size == X01 ? 'h' : 's'; in dis_AdvSIMD_vector_x_indexed_elem()
12651 case X01: in dis_AdvSIMD_vector_x_indexed_elem()
12673 HChar ch = size == X01 ? 'h' : 's'; in dis_AdvSIMD_vector_x_indexed_elem()
12702 case X01: in dis_AdvSIMD_vector_x_indexed_elem()
12731 HChar ch = size == X01 ? 'h' : 's'; in dis_AdvSIMD_vector_x_indexed_elem()
12747 case X01: in dis_AdvSIMD_vector_x_indexed_elem()
12769 HChar ch = size == X01 ? 'h' : 's'; in dis_AdvSIMD_vector_x_indexed_elem()
12827 if (ty <= X01 && op == X00 in dis_AdvSIMD_fp_compare()
12965 if (ty <= X01) { in dis_AdvSIMD_fp_conditional_select()
12968 IRType ity = ty == X01 ? Ity_F64 : Ity_F32; in dis_AdvSIMD_fp_conditional_select()
13007 if (ty <= X01 && opcode <= BITS6(0,0,0,0,1,1)) { in dis_AdvSIMD_fp_data_proc_1_source()
13012 IRType ity = ty == X01 ? Ity_F64 : Ity_F32; in dis_AdvSIMD_fp_data_proc_1_source()
13042 || (ty == X01 && (opcode == BITS6(0,0,0,1,1,1) in dis_AdvSIMD_fp_data_proc_1_source()
13117 if (ty <= X01 in dis_AdvSIMD_fp_data_proc_1_source()
13202 if (ty <= X01 && opcode <= BITS4(0,1,1,1)) { in dis_AdvSIMD_fp_data_proc_2_source()
13241 if (ty <= X01 && opcode == BITS4(1,0,0,0)) { in dis_AdvSIMD_fp_data_proc_2_source()
13285 if (ty <= X01) { in dis_AdvSIMD_fp_data_proc_3_source()
13357 if (ty <= X01 && imm5 == BITS5(0,0,0,0,0)) { in dis_AdvSIMD_fp_immediate()
13398 if (ty <= X01 && rm == X11 in dis_AdvSIMD_fp_to_from_fixedp_conv()
13458 if (ty <= X01 && rm == X00 in dis_AdvSIMD_fp_to_from_fixedp_conv()
13533 if (ty <= X01 in dis_AdvSIMD_fp_to_from_int_conv()
13651 if (ty <= X01 && rm == X00 && (op == BITS3(0,1,0) || op == BITS3(0,1,1))) { in dis_AdvSIMD_fp_to_from_int_conv()