230 #define X10 BITS2(1,0)  macro
7520       case X10:  in math_WIDEN_LO_OR_HI_LANES()
7569       case X10: amt = 32; break;  in math_WIDEN_EVEN_OR_ODD_LANES()
7705       case X10:  in math_VEC_DUP_IMM()
7918    vassert(size == X01 || size == X10); /* s or h only */  in math_SQDMULH()
8450       if (size == X11 || (size == X10 && bitQ == 0)) return False;  in dis_AdvSIMD_across_lanes()
8494       if (size == X10 && bitQ == 0) return False; // 2s case not allowed  in dis_AdvSIMD_across_lanes()
8542    if ((size == X00 || size == X10)  in dis_AdvSIMD_across_lanes()
9340       vassert(size >= X00 && size <= X10);  in dis_AdvSIMD_scalar_shift_by_imm()
9394       vassert(size == X10 || size == X11);  in dis_AdvSIMD_scalar_shift_by_imm()
9432       vassert(size == X10 || size == X11);  in dis_AdvSIMD_scalar_shift_by_imm()
9741    if (bitU == 1 && size >= X10 && opcode == BITS5(1,1,0,1,0)) {  in dis_AdvSIMD_scalar_three_same()
9782       putQReg128(dd, mkexpr(math_ZERO_ALL_EXCEPT_LOWEST_LANE(isD ? X11 : X10,  in dis_AdvSIMD_scalar_three_same()
9789    if (bitU == 1 && size >= X10 && opcode == BITS5(1,1,1,0,0)) {  in dis_AdvSIMD_scalar_three_same()
9796       putQReg128(dd, mkexpr(math_ZERO_ALL_EXCEPT_LOWEST_LANE(isD ? X11 : X10,  in dis_AdvSIMD_scalar_three_same()
9815       putQReg128(dd, mkexpr(math_ZERO_ALL_EXCEPT_LOWEST_LANE(isD ? X11 : X10,  in dis_AdvSIMD_scalar_three_same()
9831       putQReg128(dd, mkexpr(math_ZERO_ALL_EXCEPT_LOWEST_LANE(isD ? X11 : X10,  in dis_AdvSIMD_scalar_three_same()
9961    if (size >= X10) {  in dis_AdvSIMD_scalar_two_reg_misc()
9995       putQReg128(dd, mkexpr(math_ZERO_ALL_EXCEPT_LOWEST_LANE(isD ? X11 : X10,  in dis_AdvSIMD_scalar_two_reg_misc()
10123    if (size >= X10 && opcode == BITS5(1,1,1,0,1)) {  in dis_AdvSIMD_scalar_two_reg_misc()
10132       putQReg128(dd, mkexpr(math_ZERO_ALL_EXCEPT_LOWEST_LANE(isD ? X11 : X10,  in dis_AdvSIMD_scalar_two_reg_misc()
10139    if (bitU == 0 && size >= X10 && opcode == BITS5(1,1,1,1,1)) {  in dis_AdvSIMD_scalar_two_reg_misc()
10185    if (bitU == 0 && size >= X10  in dis_AdvSIMD_scalar_x_indexed_element()
10220    if (size >= X10 && opcode == BITS4(1,0,0,1)) {  in dis_AdvSIMD_scalar_x_indexed_element()
10271          case X10:  in dis_AdvSIMD_scalar_x_indexed_element()
10314          case X10:  in dis_AdvSIMD_scalar_x_indexed_element()
10749       vassert(size == X10 || size == X11);  in dis_AdvSIMD_shift_by_immediate()
10795       vassert(size == X10 || size == X11);  in dis_AdvSIMD_shift_by_immediate()
11577       IROp   opMXX = (isMIN ? mkVecMINF : mkVecMAXF)(isD ? X11 : X10);  in dis_AdvSIMD_three_same()
11633    if (bitU == 1 && size >= X10 && opcode == BITS5(1,1,0,1,0)) {  in dis_AdvSIMD_three_same()
11688    if (bitU == 1 && size >= X10 && opcode == BITS5(1,1,1,0,0)) {  in dis_AdvSIMD_three_same()
11839    if (bitU == 0 && size <= X10 && opcode == BITS5(0,0,0,0,0)) {  in dis_AdvSIMD_two_reg_misc()
12075    if (size >= X10) {  in dis_AdvSIMD_two_reg_misc()
12116    if (size >= X10 && opcode == BITS5(0,1,1,1,1)) {  in dis_AdvSIMD_two_reg_misc()
12121       IROp   op     = isFNEG ? (size == X10 ? Iop_Neg32Fx4 : Iop_Neg64Fx2)  in dis_AdvSIMD_two_reg_misc()
12122                              : (size == X10 ? Iop_Abs32Fx4 : Iop_Abs64Fx2);  in dis_AdvSIMD_two_reg_misc()
12399    if (size == X10 && opcode == BITS5(1,1,1,0,0)) {  in dis_AdvSIMD_two_reg_misc()
12452    if (size >= X10 && opcode == BITS5(1,1,1,0,1)) {  in dis_AdvSIMD_two_reg_misc()
12469    if (bitU == 1 && size >= X10 && opcode == BITS5(1,1,1,1,1)) {  in dis_AdvSIMD_two_reg_misc()
12516    if (bitU == 0 && size >= X10  in dis_AdvSIMD_vector_x_indexed_elem()
12551    if (size >= X10 && opcode == BITS4(1,0,0,1)) {  in dis_AdvSIMD_vector_x_indexed_elem()
12594          case X10:  in dis_AdvSIMD_vector_x_indexed_elem()
12653          case X10:  in dis_AdvSIMD_vector_x_indexed_elem()
12704          case X10:  in dis_AdvSIMD_vector_x_indexed_elem()
12749          case X10:  in dis_AdvSIMD_vector_x_indexed_elem()