Lines Matching refs:vassert
150 vassert(n > 1 && n < 64); in sx_to_64()
260 vassert(i < 65536); in mkU16()
266 vassert(i < 256); in mkU8()
357 vassert(isPlausibleIRType(ty)); in newTemp()
371 vassert(t1 && *t1 == IRTemp_INVALID); in newTempsV128_2()
372 vassert(t2 && *t2 == IRTemp_INVALID); in newTempsV128_2()
380 vassert(t1 && *t1 == IRTemp_INVALID); in newTempsV128_3()
381 vassert(t2 && *t2 == IRTemp_INVALID); in newTempsV128_3()
382 vassert(t3 && *t3 == IRTemp_INVALID); in newTempsV128_3()
391 vassert(t1 && *t1 == IRTemp_INVALID); in newTempsV128_4()
392 vassert(t2 && *t2 == IRTemp_INVALID); in newTempsV128_4()
393 vassert(t3 && *t3 == IRTemp_INVALID); in newTempsV128_4()
394 vassert(t4 && *t4 == IRTemp_INVALID); in newTempsV128_4()
405 vassert(t1 && *t1 == IRTemp_INVALID); in newTempsV128_7()
406 vassert(t2 && *t2 == IRTemp_INVALID); in newTempsV128_7()
407 vassert(t3 && *t3 == IRTemp_INVALID); in newTempsV128_7()
408 vassert(t4 && *t4 == IRTemp_INVALID); in newTempsV128_7()
409 vassert(t5 && *t5 == IRTemp_INVALID); in newTempsV128_7()
410 vassert(t6 && *t6 == IRTemp_INVALID); in newTempsV128_7()
411 vassert(t7 && *t7 == IRTemp_INVALID); in newTempsV128_7()
587 vassert(size < 4); in mkVecADD()
594 vassert(size < 4); in mkVecQADDU()
601 vassert(size < 4); in mkVecQADDS()
609 vassert(size < 4); in mkVecQADDEXTSUSATUU()
617 vassert(size < 4); in mkVecQADDEXTUSSATSS()
624 vassert(size < 4); in mkVecSUB()
631 vassert(size < 4); in mkVecQSUBU()
638 vassert(size < 4); in mkVecQSUBS()
645 vassert(size < 4); in mkVecSARN()
652 vassert(size < 4); in mkVecSHRN()
659 vassert(size < 4); in mkVecSHLN()
667 vassert(size < 4); in mkVecCATEVENLANES()
675 vassert(size < 4); in mkVecCATODDLANES()
683 vassert(size < 4); in mkVecINTERLEAVELO()
691 vassert(size < 4); in mkVecINTERLEAVEHI()
698 vassert(size < 4); in mkVecMAXU()
705 vassert(size < 4); in mkVecMAXS()
712 vassert(size < 4); in mkVecMINU()
719 vassert(size < 4); in mkVecMINS()
726 vassert(size < 3); in mkVecMUL()
733 vassert(sizeNarrow < 3); in mkVecMULLU()
740 vassert(sizeNarrow < 3); in mkVecMULLS()
747 vassert(sizeNarrow < 3); in mkVecQDMULLS()
754 vassert(size < 4); in mkVecCMPEQ()
761 vassert(size < 4); in mkVecCMPGTU()
768 vassert(size < 4); in mkVecCMPGTS()
775 vassert(size < 4); in mkVecABS()
783 vassert(size < 4); in mkVecZEROHIxxOFV128()
798 vassert(size < 4); in mkVecQDMULHIS()
805 vassert(size < 4); in mkVecQRDMULHIS()
813 vassert(size < 4); in mkVecQANDUQSH()
821 vassert(size < 4); in mkVecQANDSQSH()
829 vassert(size < 4); in mkVecQANDUQRSH()
837 vassert(size < 4); in mkVecQANDSQRSH()
844 vassert(size < 4); in mkVecSHU()
851 vassert(size < 4); in mkVecSHS()
858 vassert(size < 4); in mkVecRSHU()
865 vassert(size < 4); in mkVecRSHS()
873 vassert(sizeNarrow < 4); in mkVecNARROWUN()
881 vassert(sizeNarrow < 4); in mkVecQNARROWUNSU()
889 vassert(sizeNarrow < 4); in mkVecQNARROWUNSS()
897 vassert(sizeNarrow < 4); in mkVecQNARROWUNUU()
905 vassert(sizeNarrow < 4); in mkVecQANDqshrNNARROWUU()
913 vassert(sizeNarrow < 4); in mkVecQANDqsarNNARROWSS()
921 vassert(sizeNarrow < 4); in mkVecQANDqsarNNARROWSU()
929 vassert(sizeNarrow < 4); in mkVecQANDqrshrNNARROWUU()
937 vassert(sizeNarrow < 4); in mkVecQANDqrsarNNARROWSS()
945 vassert(sizeNarrow < 4); in mkVecQANDqrsarNNARROWSU()
953 vassert(size < 4); in mkVecQSHLNSATUU()
961 vassert(size < 4); in mkVecQSHLNSATSS()
969 vassert(size < 4); in mkVecQSHLNSATSU()
976 vassert(size < 4); in mkVecADDF()
983 vassert(size < 4); in mkVecMAXF()
990 vassert(size < 4); in mkVecMINF()
1002 vassert(ty == Ity_I32); in mathROR()
1005 vassert(w != 0); in mathROR()
1006 vassert(imm < w); in mathROR()
1025 vassert(ty == Ity_I32); in mathREPLICATE()
1028 vassert(w != 0); in mathREPLICATE()
1029 vassert(imm < w); in mathREPLICATE()
1189 default: vassert(0); in offsetIReg64()
1200 vassert(iregNo < 32); in nameIReg64orZR()
1214 vassert(iregNo < 31); in nameIReg64orSP()
1220 vassert(iregNo < 32); in getIReg64orSP()
1229 vassert(iregNo < 31); in getIReg64orZR()
1235 vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I64); in putIReg64orSP()
1241 vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I64); in putIReg64orZR()
1245 vassert(iregNo < 31); in putIReg64orZR()
1251 vassert(iregNo < 32); in nameIReg32orZR()
1265 vassert(iregNo < 31); in nameIReg32orSP()
1271 vassert(iregNo < 32); in getIReg32orSP()
1281 vassert(iregNo < 31); in getIReg32orZR()
1288 vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I32); in putIReg32orSP()
1294 vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I32); in putIReg32orZR()
1298 vassert(iregNo < 31); in putIReg32orZR()
1304 vassert(is64 == True || is64 == False); in nameIRegOrSP()
1310 vassert(is64 == True || is64 == False); in nameIRegOrZR()
1316 vassert(is64 == True || is64 == False); in getIRegOrZR()
1322 vassert(is64 == True || is64 == False); in putIRegOrZR()
1328 vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I64); in putPC()
1372 default: vassert(0); in offsetQReg128()
1379 vassert(qregNo < 32); in putQReg128()
1380 vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_V128); in putQReg128()
1387 vassert(qregNo < 32); in getQReg128()
1404 default: vassert(0); in preferredVectorSubTypeFromSize()
1413 vassert(host_endness == VexEndnessLE); in offsetQRegLane()
1428 vassert(laneSzB > 0); in offsetQRegLane()
1431 vassert(maxOff < 16); in offsetQRegLane()
1445 vassert(0); // Other cases are probably invalid in putQRegLO()
1461 vassert(0); // Other cases are ATC in getQRegLO()
1493 vassert(qregNo < 32); in nameQRegLO()
1500 default: vassert(0); in nameQRegLO()
1530 vassert(0); // Other cases are plain wrong in putQRegHI64()
1547 vassert(0); // Other cases are ATC in putQRegLane()
1561 vassert(0); // Other cases are ATC in getQRegLane()
1718 vassert(typeOfIRExpr(irsb->tyenv, cond) == Ity_I64); in mk_arm64g_calculate_condition_dyn()
1762 vassert(cond >= 0 && cond <= 15); in mk_arm64g_calculate_condition()
1843 vassert(typeOfIRTemp(irsb->tyenv, t_dep1 == Ity_I64)); in setFlags_D1_D2_ND()
1844 vassert(typeOfIRTemp(irsb->tyenv, t_dep2 == Ity_I64)); in setFlags_D1_D2_ND()
1845 vassert(typeOfIRTemp(irsb->tyenv, t_ndep == Ity_I64)); in setFlags_D1_D2_ND()
1846 vassert(cc_op >= ARM64G_CC_OP_COPY && cc_op < ARM64G_CC_OP_NUMBER); in setFlags_D1_D2_ND()
1875 else { vassert(0); } in setFlags_ADD_SUB()
1904 else { vassert(0); } in setFlags_ADC_SBC()
1935 else { vassert(0); } in setFlags_ADD_SUB_conditionally()
2043 vassert(sh >= 1 && sh <= 63); in math_SWAPHELPER()
2130 vassert(0); in math_DUP_TO_64()
2164 vassert(0); in math_DUP_TO_V128()
2174 vassert(0); in math_MAYBE_ZERO_HI64()
2276 vassert(width > 0 && width <= 64); in dbm_ROR()
2277 vassert(rot >= 0 && rot < width); in dbm_ROR()
2323 vassert(x == 0); in dbm_highestSetBit()
2332 vassert(immN < (1ULL << 1)); in dbm_DecodeBitMasks()
2333 vassert(imms < (1ULL << 6)); in dbm_DecodeBitMasks()
2334 vassert(immr < (1ULL << 6)); in dbm_DecodeBitMasks()
2335 vassert(immediate == False || immediate == True); in dbm_DecodeBitMasks()
2336 vassert(M == 32 || M == 64); in dbm_DecodeBitMasks()
2340 vassert(len <= 6); in dbm_DecodeBitMasks()
2341 vassert(M >= (1 << len)); in dbm_DecodeBitMasks()
2343 vassert(len >= 1 && len <= 6); in dbm_DecodeBitMasks()
2346 vassert(levels >= 1 && levels <= 63); in dbm_DecodeBitMasks()
2358 vassert(2 <= esize && esize <= 64); in dbm_DecodeBitMasks()
2363 vassert(S >= 0 && S <= 63); in dbm_DecodeBitMasks()
2364 vassert(esize >= (S+1)); in dbm_DecodeBitMasks()
2371 vassert(esize >= (d+1)); in dbm_DecodeBitMasks()
2372 vassert(d >= 0 && d <= 63); in dbm_DecodeBitMasks()
2378 if (esize != 64) vassert(elem_s < (1ULL << esize)); in dbm_DecodeBitMasks()
2379 if (esize != 64) vassert(elem_d < (1ULL << esize)); in dbm_DecodeBitMasks()
2416 vassert(sh <= 1); in dis_ARM64_data_processing_immediate()
2507 vassert(op < 4); in dis_ARM64_data_processing_immediate()
2561 vassert(imm64 < 0x100000000ULL); in dis_ARM64_data_processing_immediate()
2592 vassert(hw <= 1); in dis_ARM64_data_processing_immediate()
2604 vassert(0); in dis_ARM64_data_processing_immediate()
2647 vassert(0); in dis_ARM64_data_processing_immediate()
2712 vassert(imm6 > 0 && imm6 < szBits); in dis_ARM64_data_processing_immediate()
2741 default: vassert(0); in nameSH()
2758 vassert(sh_how < 4); in getShiftedIRegOrZR()
2759 vassert(sh_amt < (is64 ? 64 : 32)); in getShiftedIRegOrZR()
2778 vassert(0); in getShiftedIRegOrZR()
2937 default: vassert(0); in dis_ARM64_data_processing_register()
2948 vassert(((bN << 2) | INSN(30,29)) < 8); in dis_ARM64_data_processing_register()
3048 vassert(0); in dis_ARM64_data_processing_register()
3138 vassert(shSX >= 32); in dis_ARM64_data_processing_register()
3143 vassert(0); in dis_ARM64_data_processing_register()
3301 default: vassert(0); in dis_ARM64_data_processing_register()
3306 vassert(math); in dis_ARM64_data_processing_register()
3406 default: vassert(0); in dis_ARM64_data_processing_register()
3431 vassert(op < 4); in dis_ARM64_data_processing_register()
3613 vassert(0); in math_INTERLEAVE2_128()
3808 vassert(0); in math_INTERLEAVE3_128()
3873 vassert(0); in math_INTERLEAVE4_128()
3928 vassert(0); in math_DEINTERLEAVE2_128()
4098 vassert(0); in math_DEINTERLEAVE3_128()
4166 vassert(0); in math_DEINTERLEAVE4_128()
4194 vassert(0); in math_get_doubler_and_halver()
4219 vassert(laneSzBlg2 >= 0 && laneSzBlg2 <= 2); in math_INTERLEAVE2_64()
4250 vassert(laneSzBlg2 >= 0 && laneSzBlg2 <= 2); in math_INTERLEAVE3_64()
4286 vassert(laneSzBlg2 >= 0 && laneSzBlg2 <= 2); in math_INTERLEAVE4_64()
4332 vassert(laneSzBlg2 >= 0 && laneSzBlg2 <= 2); in math_DEINTERLEAVE2_64()
4364 vassert(laneSzBlg2 >= 0 && laneSzBlg2 <= 2); in math_DEINTERLEAVE3_64()
4400 vassert(laneSzBlg2 >= 0 && laneSzBlg2 <= 2); in math_DEINTERLEAVE4_64()
4515 default: vassert(0); in gen_indexed_EA()
4559 vassert(rhs); in gen_indexed_EA()
4589 vassert(0); in gen_narrowing_store()
4614 vassert(0); in gen_zwidening_load()
4625 vassert(bitQ <= 1 && size <= 3); in nameArr_Q_SZ()
4629 vassert(ix < 8); in nameArr_Q_SZ()
4666 vassert(szLg2 < 4); in dis_ARM64_load_store()
4738 vassert(0); /* NOTREACHED */ in dis_ARM64_load_store()
4782 vassert(0); in dis_ARM64_load_store()
4842 vassert(0); /* NOTREACHED */ in dis_ARM64_load_store()
4882 vassert(bL == 0 && bX == 0); in dis_ARM64_load_store()
4905 vassert(0); in dis_ARM64_load_store()
4998 vassert(0); in dis_ARM64_load_store()
5033 vassert(bitX == 0); in dis_ARM64_load_store()
5059 vassert(0); in dis_ARM64_load_store()
5141 vassert(0); in dis_ARM64_load_store()
5216 vassert(0); in dis_ARM64_load_store()
5280 vassert(0); /* NOTREACHED */ in dis_ARM64_load_store()
5288 default: vassert(0); in dis_ARM64_load_store()
5347 vassert(0); in dis_ARM64_load_store()
5431 vassert(0); in dis_ARM64_load_store()
5717 default: vassert(0); in dis_ARM64_load_store()
5727 default: vassert(0); in dis_ARM64_load_store()
5742 default: vassert(0); in dis_ARM64_load_store()
5760 default: vassert(0); in dis_ARM64_load_store()
5797 vassert(0); in dis_ARM64_load_store()
5813 default: vassert(0); in dis_ARM64_load_store()
5828 default: vassert(0); in dis_ARM64_load_store()
5928 default: vassert(0); in dis_ARM64_load_store()
5938 default: vassert(0); in dis_ARM64_load_store()
5955 default: vassert(0); in dis_ARM64_load_store()
5990 vassert(0); in dis_ARM64_load_store()
6005 default: vassert(0); in dis_ARM64_load_store()
6124 vassert(0); in dis_ARM64_load_store()
6280 vassert(0); in dis_ARM64_load_store()
6320 vassert(szBlg2 < 4); in dis_ARM64_load_store()
6372 vassert(szBlg2 < 4); in dis_ARM64_load_store()
6453 vassert(dres->whatNext == Dis_Continue); in dis_ARM64_branch_etc()
6454 vassert(dres->len == 4); in dis_ARM64_branch_etc()
6455 vassert(dres->continueAt == 0); in dis_ARM64_branch_etc()
6456 vassert(dres->jk_StopHere == Ijk_INVALID); in dis_ARM64_branch_etc()
6725 vassert(archinfo->arm64_dMinLine_lg2_szB >= 2 in dis_ARM64_branch_etc()
6764 vassert(archinfo->arm64_iMinLine_lg2_szB >= 2 in dis_ARM64_branch_etc()
6795 vassert(archinfo->arm64_dMinLine_lg2_szB >= 2 in dis_ARM64_branch_etc()
6830 vassert(opc <= 2 && CRm <= 15); in dis_ARM64_branch_etc()
6969 vassert(bit <= 1 && N >= 1 && N < 64); in Replicate()
6980 vassert(0 == (bits32 & ~0xFFFFFFFFULL)); in Replicate32x2()
6986 vassert(0 == (bits16 & ~0xFFFFULL)); in Replicate16x4()
6992 vassert(0 == (bits8 & ~0xFFULL)); in Replicate8x8()
7002 vassert(imm8 <= 0xFF); in VFPExpandImm()
7003 vassert(N == 32 || N == 64); in VFPExpandImm()
7013 vassert(sign < (1ULL << 1)); in VFPExpandImm()
7014 vassert(exp < (1ULL << E)); in VFPExpandImm()
7015 vassert(frac < (1ULL << F)); in VFPExpandImm()
7016 vassert(1 + E + F == N); in VFPExpandImm()
7027 vassert(op <= 1); in AdvSIMDExpandImm()
7028 vassert(cmode <= 15); in AdvSIMDExpandImm()
7029 vassert(imm8 <= 255); in AdvSIMDExpandImm()
7092 vassert(0); in AdvSIMDExpandImm()
7110 vassert(bitQ == True || bitQ == False); in getLaneInfo_Q_SZ()
7111 vassert(bitSZ == True || bitSZ == False); in getLaneInfo_Q_SZ()
7145 vassert(immh < (1<<4)); in getLaneInfo_IMMH_IMMB()
7146 vassert(immb < (1<<3)); in getLaneInfo_IMMH_IMMB()
7371 vassert(0); in math_FOLDV()
7381 vassert(len >= 0 && len <= 3); in math_TBL_TBX()
7419 vassert(tabent >= 0 && tabent < 4); in math_TBL_TBX()
7488 vassert(size <= 3); in math_ABD()
7548 vassert(0); in math_WIDEN_LO_OR_HI_LANES()
7572 default: vassert(0); in math_WIDEN_EVEN_OR_ODD_LANES()
7602 vassert(size <= 3); in math_DUP_VEC_ELEM()
7609 vassert(ix <= 15); in math_DUP_VEC_ELEM()
7625 vassert(0); in math_DUP_VEC_ELEM()
7701 vassert(imm <= 0xFFFFULL); in math_VEC_DUP_IMM()
7706 vassert(imm <= 0xFFFFFFFFULL); in math_VEC_DUP_IMM()
7714 vassert(0); in math_VEC_DUP_IMM()
7792 vassert(size < 4); in math_ZERO_ALL_EXCEPT_LOWEST_LANE()
7816 vassert(res && *res == IRTemp_INVALID); in math_MULL_ACC()
7817 vassert(size <= 2); in math_MULL_ACC()
7818 vassert(mas == 'm' || mas == 'a' || mas == 's'); in math_MULL_ACC()
7819 if (mas == 'm') vassert(vecD == IRTemp_INVALID); in math_MULL_ACC()
7847 vassert(size <= 2); in math_SQDMULL_ACC()
7848 vassert(mas == 'm' || mas == 'a' || mas == 's'); in math_SQDMULL_ACC()
7856 vassert(sat2q && *sat2q == IRTemp_INVALID); in math_SQDMULL_ACC()
7857 vassert(sat2n && *sat2n == IRTemp_INVALID); in math_SQDMULL_ACC()
7894 vassert(sizeNarrow <= 2); in math_MULLS()
7918 vassert(size == X01 || size == X10); /* s or h only */ in math_SQDMULH()
7962 vassert(size <= 3); in math_QSHL_IMM()
7964 vassert(shift < laneBits); in math_QSHL_IMM()
7982 vassert(rshift >= 1 && rshift < laneBits); in math_QSHL_IMM()
8001 vassert(rshift >= 0 && rshift < laneBits-1); in math_QSHL_IMM()
8031 vassert(rshift >= 1 && rshift < laneBits); in math_QSHL_IMM()
8038 vassert(0); in math_QSHL_IMM()
8049 vassert(size <= 3); in math_RHADD()
8104 vassert(opZHI == Iop_ZeroHI64ofV128 in updateQCFLAGwithDifferenceZHI()
8144 vassert(rearrL && *rearrL == IRTemp_INVALID); in math_REARRANGE_FOR_FLOATING_PAIRWISE()
8145 vassert(rearrR && *rearrR == IRTemp_INVALID); in math_REARRANGE_FOR_FLOATING_PAIRWISE()
8150 vassert(bitQ == 1); in math_REARRANGE_FOR_FLOATING_PAIRWISE()
8160 vassert(!isD && bitQ == 0); in math_REARRANGE_FOR_FLOATING_PAIRWISE()
8177 vassert(n >= 2 && n <= 64); in two_to_the_minus()
8187 vassert(n >= 2 && n <= 64); in two_to_the_plus()
8228 vassert(imm4 >= 1 && imm4 <= 15); in dis_AdvSIMD_EXT()
8239 vassert(imm4 >= 1 && imm4 <= 7); in dis_AdvSIMD_EXT()
8299 vassert(i < 4); in dis_AdvSIMD_TBL_TBX()
8492 vassert(ix >= 1 && ix <= 5); in dis_AdvSIMD_across_lanes()
8505 vassert(size < 3); in dis_AdvSIMD_across_lanes()
8514 default: vassert(0); in dis_AdvSIMD_across_lanes()
8516 vassert(op != Iop_INVALID && nm != NULL); in dis_AdvSIMD_across_lanes()
8695 vassert(laneNo < 16); in dis_AdvSIMD_copy()
8789 vassert(laneNo < 16); in dis_AdvSIMD_copy()
8840 vassert(ix1 < 16); in dis_AdvSIMD_copy()
8841 vassert(ix2 < 16); in dis_AdvSIMD_copy()
8968 vassert(1 == (isMOV ? 1 : 0) + (isMVN ? 1 : 0) in dis_AdvSIMD_modified_immediate()
9061 vassert(laneNo < 16); in dis_AdvSIMD_scalar_copy()
9188 vassert(sh >= 1 && sh <= 64); in dis_AdvSIMD_scalar_shift_by_imm()
9198 vassert(!isU); in dis_AdvSIMD_scalar_shift_by_imm()
9221 vassert(sh >= 1 && sh <= 64); in dis_AdvSIMD_scalar_shift_by_imm()
9223 vassert(sh >= 1 && sh <= 64); in dis_AdvSIMD_scalar_shift_by_imm()
9243 vassert(sh >= 1 && sh <= 64); in dis_AdvSIMD_scalar_shift_by_imm()
9263 vassert(sh >= 0 && sh < 64); in dis_AdvSIMD_scalar_shift_by_imm()
9275 vassert(sh >= 0 && sh < 64); in dis_AdvSIMD_scalar_shift_by_imm()
9301 vassert(size >= 0 && size <= 3); in dis_AdvSIMD_scalar_shift_by_imm()
9306 vassert(shift >= 0 && shift < lanebits); in dis_AdvSIMD_scalar_shift_by_imm()
9311 else vassert(0); in dis_AdvSIMD_scalar_shift_by_imm()
9340 vassert(size >= X00 && size <= X10); in dis_AdvSIMD_scalar_shift_by_imm()
9341 vassert(shift >= 1 && shift <= (8 << size)); in dis_AdvSIMD_scalar_shift_by_imm()
9363 else vassert(0); in dis_AdvSIMD_scalar_shift_by_imm()
9392 vassert(ok); in dis_AdvSIMD_scalar_shift_by_imm()
9394 vassert(size == X10 || size == X11); in dis_AdvSIMD_scalar_shift_by_imm()
9397 vassert(fbits >= 1 && fbits <= (isD ? 64 : 32)); in dis_AdvSIMD_scalar_shift_by_imm()
9430 vassert(ok); in dis_AdvSIMD_scalar_shift_by_imm()
9432 vassert(size == X10 || size == X11); in dis_AdvSIMD_scalar_shift_by_imm()
9435 vassert(fbits >= 1 && fbits <= (isD ? 64 : 32)); in dis_AdvSIMD_scalar_shift_by_imm()
9488 vassert(size < 4); in dis_AdvSIMD_scalar_three_different()
9502 default: vassert(0); in dis_AdvSIMD_scalar_three_different()
9504 vassert(ks >= 0 && ks <= 2); in dis_AdvSIMD_scalar_three_different()
9506 vassert(size <= 2); in dis_AdvSIMD_scalar_three_different()
9518 vassert(sat1q != IRTemp_INVALID && sat1n != IRTemp_INVALID); in dis_AdvSIMD_scalar_three_different()
9557 vassert(size < 4); in dis_AdvSIMD_scalar_three_same()
9863 vassert(size < 4); in dis_AdvSIMD_scalar_two_reg_misc()
9989 default: vassert(0); in dis_AdvSIMD_scalar_two_reg_misc()
10008 vassert(size < 3); in dis_AdvSIMD_scalar_two_reg_misc()
10021 else vassert(0); in dis_AdvSIMD_scalar_two_reg_misc()
10081 default: vassert(0); in dis_AdvSIMD_scalar_two_reg_misc()
10182 vassert(size < 4); in dis_AdvSIMD_scalar_x_indexed_element()
10183 vassert(bitH < 2 && bitM < 2 && bitL < 2); in dis_AdvSIMD_scalar_x_indexed_element()
10195 vassert(index < (isD ? 2 : 4)); in dis_AdvSIMD_scalar_x_indexed_element()
10229 vassert(index < (isD ? 2 : 4)); in dis_AdvSIMD_scalar_x_indexed_element()
10261 default: vassert(0); in dis_AdvSIMD_scalar_x_indexed_element()
10263 vassert(ks >= 0 && ks <= 2); in dis_AdvSIMD_scalar_x_indexed_element()
10276 vassert(0); in dis_AdvSIMD_scalar_x_indexed_element()
10278 vassert(mm < 32 && ix < 16); in dis_AdvSIMD_scalar_x_indexed_element()
10290 vassert(sat1q != IRTemp_INVALID && sat1n != IRTemp_INVALID); in dis_AdvSIMD_scalar_x_indexed_element()
10319 vassert(0); in dis_AdvSIMD_scalar_x_indexed_element()
10321 vassert(mm < 32 && ix < 16); in dis_AdvSIMD_scalar_x_indexed_element()
10382 vassert(size >= 0 && size <= 3); in dis_AdvSIMD_shift_by_immediate()
10384 vassert(shift >= 1 && shift <= lanebits); in dis_AdvSIMD_shift_by_immediate()
10394 vassert(!isU); in dis_AdvSIMD_shift_by_immediate()
10431 vassert(size >= 0 && size <= 3); in dis_AdvSIMD_shift_by_immediate()
10433 vassert(shift >= 1 && shift <= lanebits); in dis_AdvSIMD_shift_by_immediate()
10469 vassert(size >= 0 && size <= 3); in dis_AdvSIMD_shift_by_immediate()
10471 vassert(shift >= 1 && shift <= lanebits); in dis_AdvSIMD_shift_by_immediate()
10511 vassert(size >= 0 && size <= 3); in dis_AdvSIMD_shift_by_immediate()
10516 vassert(shift >= 0 && shift < lanebits); in dis_AdvSIMD_shift_by_immediate()
10554 vassert(size >= 0 && size <= 3); in dis_AdvSIMD_shift_by_immediate()
10559 vassert(shift >= 0 && shift < lanebits); in dis_AdvSIMD_shift_by_immediate()
10564 else vassert(0); in dis_AdvSIMD_shift_by_immediate()
10591 vassert(shift >= 1); in dis_AdvSIMD_shift_by_immediate()
10624 vassert(shift >= 1 && shift <= (8 << size)); in dis_AdvSIMD_shift_by_immediate()
10646 else vassert(0); in dis_AdvSIMD_shift_by_immediate()
10699 vassert(sh < 32); /* so 32-sh is 1..32 */ in dis_AdvSIMD_shift_by_immediate()
10708 vassert(sh < 16); /* so 16-sh is 1..16 */ in dis_AdvSIMD_shift_by_immediate()
10717 vassert(sh < 8); /* so 8-sh is 1..8 */ in dis_AdvSIMD_shift_by_immediate()
10724 vassert(immh == 0); in dis_AdvSIMD_shift_by_immediate()
10747 vassert(ok); in dis_AdvSIMD_shift_by_immediate()
10749 vassert(size == X10 || size == X11); in dis_AdvSIMD_shift_by_immediate()
10754 vassert(fbits >= 1 && fbits <= (isD ? 64 : 32)); in dis_AdvSIMD_shift_by_immediate()
10764 vassert(nLanes == 2 || nLanes == 4); in dis_AdvSIMD_shift_by_immediate()
10793 vassert(ok); in dis_AdvSIMD_shift_by_immediate()
10795 vassert(size == X10 || size == X11); in dis_AdvSIMD_shift_by_immediate()
10800 vassert(fbits >= 1 && fbits <= (isD ? 64 : 32)); in dis_AdvSIMD_shift_by_immediate()
10810 vassert(nLanes == 2 || nLanes == 4); in dis_AdvSIMD_shift_by_immediate()
10858 vassert(size < 4); in dis_AdvSIMD_three_different()
10868 vassert(size <= 2); in dis_AdvSIMD_three_different()
10894 vassert(size <= 2); in dis_AdvSIMD_three_different()
10919 vassert(size <= 2); in dis_AdvSIMD_three_different()
10958 vassert(size <= 2); in dis_AdvSIMD_three_different()
10992 default: vassert(0); in dis_AdvSIMD_three_different()
10994 vassert(ks >= 0 && ks <= 2); in dis_AdvSIMD_three_different()
10996 vassert(size <= 2); in dis_AdvSIMD_three_different()
11029 default: vassert(0); in dis_AdvSIMD_three_different()
11031 vassert(ks >= 0 && ks <= 2); in dis_AdvSIMD_three_different()
11033 vassert(size <= 2); in dis_AdvSIMD_three_different()
11044 vassert(sat1q != IRTemp_INVALID && sat1n != IRTemp_INVALID); in dis_AdvSIMD_three_different()
11101 vassert(size < 4); in dis_AdvSIMD_three_same()
11257 vassert(0); in dis_AdvSIMD_three_same()
11392 vassert(size <= 2); in dis_AdvSIMD_three_same()
11780 vassert(size <= 1); in dis_AdvSIMD_three_same()
11837 vassert(size < 4); in dis_AdvSIMD_two_reg_misc()
11845 vassert(size <= 2); in dis_AdvSIMD_two_reg_misc()
11951 vassert(size <= 2); in dis_AdvSIMD_two_reg_misc()
12103 default: vassert(0); in dis_AdvSIMD_two_reg_misc()
12135 vassert(size < 3); in dis_AdvSIMD_two_reg_misc()
12155 vassert(size < 3); in dis_AdvSIMD_two_reg_misc()
12169 else vassert(0); in dis_AdvSIMD_two_reg_misc()
12279 vassert(ix >= 1 && ix <= 8); in dis_AdvSIMD_two_reg_misc()
12318 default: vassert(0); in dis_AdvSIMD_two_reg_misc()
12371 default: vassert(0); in dis_AdvSIMD_two_reg_misc()
12437 vassert(ok); /* the 'if' above should ensure this */ in dis_AdvSIMD_two_reg_misc()
12513 vassert(size < 4); in dis_AdvSIMD_vector_x_indexed_elem()
12514 vassert(bitH < 2 && bitM < 2 && bitL < 2); in dis_AdvSIMD_vector_x_indexed_elem()
12527 vassert(index < (isD ? 2 : 4)); in dis_AdvSIMD_vector_x_indexed_elem()
12561 vassert(index < (isD ? 2 : 4)); in dis_AdvSIMD_vector_x_indexed_elem()
12599 vassert(0); in dis_AdvSIMD_vector_x_indexed_elem()
12601 vassert(mm < 32 && ix < 16); in dis_AdvSIMD_vector_x_indexed_elem()
12641 default: vassert(0); in dis_AdvSIMD_vector_x_indexed_elem()
12643 vassert(ks >= 0 && ks <= 2); in dis_AdvSIMD_vector_x_indexed_elem()
12658 vassert(0); in dis_AdvSIMD_vector_x_indexed_elem()
12660 vassert(mm < 32 && ix < 16); in dis_AdvSIMD_vector_x_indexed_elem()
12693 default: vassert(0); in dis_AdvSIMD_vector_x_indexed_elem()
12695 vassert(ks >= 0 && ks <= 2); in dis_AdvSIMD_vector_x_indexed_elem()
12709 vassert(0); in dis_AdvSIMD_vector_x_indexed_elem()
12711 vassert(mm < 32 && ix < 16); in dis_AdvSIMD_vector_x_indexed_elem()
12722 vassert(sat1q != IRTemp_INVALID && sat1n != IRTemp_INVALID); in dis_AdvSIMD_vector_x_indexed_elem()
12754 vassert(0); in dis_AdvSIMD_vector_x_indexed_elem()
12756 vassert(mm < 32 && ix < 16); in dis_AdvSIMD_vector_x_indexed_elem()
12825 vassert(ty < 4); in dis_AdvSIMD_fp_compare()
12901 vassert(ty < 4 && op <= 1); in dis_AdvSIMD_fp_conditional_compare()
13030 vassert(0); in dis_AdvSIMD_fp_data_proc_1_source()
13223 default: vassert(0); in dis_AdvSIMD_fp_data_proc_2_source()
13283 vassert(ty < 4); in dis_AdvSIMD_fp_data_proc_3_source()
13322 default: vassert(0); in dis_AdvSIMD_fp_data_proc_3_source()
13361 vassert(0 == (imm & 0xFFFFFFFF00000000ULL)); in dis_AdvSIMD_fp_immediate()
13416 vassert(fbits >= 1 && fbits <= (isI64 ? 64 : 32)); in dis_AdvSIMD_fp_to_from_fixedp_conv()
13467 vassert(fbits >= 1 && fbits <= (isI64 ? 64 : 32)); in dis_AdvSIMD_fp_to_from_fixedp_conv()
13550 default: vassert(0); in dis_AdvSIMD_fp_to_from_int_conv()
13553 vassert(op == BITS3(1,0,0) || op == BITS3(1,0,1)); in dis_AdvSIMD_fp_to_from_int_conv()
13556 default: vassert(0); in dis_AdvSIMD_fp_to_from_int_conv()
13559 vassert(irrm != 8); in dis_AdvSIMD_fp_to_from_int_conv()
13572 vassert(ix < 8); in dis_AdvSIMD_fp_to_from_int_conv()
13692 vassert(bitSF == 1); in dis_AdvSIMD_fp_to_from_int_conv()
13734 vassert(0); in dis_AdvSIMD_fp_to_from_int_conv()
13866 vassert(0 == (guest_PC_curr_instr & 3ULL)); in disInstr_ARM64_WRK()
13981 vassert(0); /* Can't happen */ in disInstr_ARM64_WRK()
13987 vassert(dres->whatNext == Dis_Continue); in disInstr_ARM64_WRK()
13988 vassert(dres->len == 4); in disInstr_ARM64_WRK()
13989 vassert(dres->continueAt == 0); in disInstr_ARM64_WRK()
13990 vassert(dres->jk_StopHere == Ijk_INVALID); in disInstr_ARM64_WRK()
14023 vassert(guest_arch == VexArchARM64); in disInstr_ARM64()
14031 vassert((archinfo->arm64_dMinLine_lg2_szB - 2) <= 15); in disInstr_ARM64()
14032 vassert((archinfo->arm64_iMinLine_lg2_szB - 2) <= 15); in disInstr_ARM64()
14041 vassert(dres.len == 4 || dres.len == 20); in disInstr_ARM64()
14053 vassert(0); in disInstr_ARM64()