Lines Matching refs:vassert
119 vassert(r >= 0 && r < 16); in ppHRegAMD64()
124 vassert(r >= 0 && r < 16); in ppHRegAMD64()
148 vassert(r >= 0 && r < 16); in ppHRegAMD64_lo32()
200 vassert(shift >= 0 && shift <= 3); in AMD64AMode_IRRS()
610 vassert(op != Aalu_MUL); in AMD64Instr_Alu64M()
651 default: vassert(0); in AMD64Instr_Alu32R()
668 vassert(sz == 4 || sz == 8); in AMD64Instr_Div()
685 vassert(regparms >= 0 && regparms <= 6); in AMD64Instr_Call()
686 vassert(is_sane_RetLoc(rloc)); in AMD64Instr_Call()
726 vassert(cond != Acc_ALWAYS); in AMD64Instr_CMov64()
737 vassert(cond != Acc_ALWAYS && (szB == 4 || szB == 8)); in AMD64Instr_CLoad()
748 vassert(cond != Acc_ALWAYS && (szB == 4 || szB == 8)); in AMD64Instr_CStore()
767 vassert(szSmall == 1 || szSmall == 2 || szSmall == 4); in AMD64Instr_LoadEX()
776 vassert(sz == 1 || sz == 2 || sz == 4); in AMD64Instr_Store()
804 vassert(sz == 8 || sz == 4 || sz == 2 || sz == 1); in AMD64Instr_ACAS()
812 vassert(sz == 8 || sz == 4); in AMD64Instr_DACAS()
821 vassert(nregs >= 1 && nregs <= 7); in AMD64Instr_A87Free()
831 vassert(szB == 8 || szB == 4); in AMD64Instr_A87PushPop()
868 vassert(sz == 4 || sz == 8); in AMD64Instr_SseUComIS()
878 vassert(szS == 4 || szS == 8); in AMD64Instr_SseSI2SF()
879 vassert(szD == 4 || szD == 8); in AMD64Instr_SseSI2SF()
889 vassert(szS == 4 || szS == 8); in AMD64Instr_SseSF2SI()
890 vassert(szD == 4 || szD == 8); in AMD64Instr_SseSF2SI()
910 vassert(sz == 4 || sz == 8 || sz == 16); in AMD64Instr_SseLdSt()
921 vassert(cond != Acc_ALWAYS); in AMD64Instr_SseCStore()
932 vassert(cond != Acc_ALWAYS); in AMD64Instr_SseCLoad()
942 vassert(sz == 4 || sz == 8); in AMD64Instr_SseLdzLO()
951 vassert(op != Asse_MOV); in AMD64Instr_Sse32Fx4()
960 vassert(op != Asse_MOV); in AMD64Instr_Sse32FLo()
969 vassert(op != Asse_MOV); in AMD64Instr_Sse64Fx2()
978 vassert(op != Asse_MOV); in AMD64Instr_Sse64FLo()
995 vassert(cond != Acc_ALWAYS); in AMD64Instr_SseCMov()
1004 vassert(order >= 0 && order <= 0xFF); in AMD64Instr_SseShuf()
1040 vassert(mode64 == True); in ppAMD64Instr()
1281 default: vassert(0); in ppAMD64Instr()
1397 vassert(mode64 == True); in getRegUsage_AMD64Instr()
1435 vassert(i->Ain.Alu32R.op != Aalu_MOV); in getRegUsage_AMD64Instr()
1622 vassert(i->Ain.Sse32Fx4.op != Asse_MOV); in getRegUsage_AMD64Instr()
1631 vassert(i->Ain.Sse32FLo.op != Asse_MOV); in getRegUsage_AMD64Instr()
1640 vassert(i->Ain.Sse64Fx2.op != Asse_MOV); in getRegUsage_AMD64Instr()
1649 vassert(i->Ain.Sse64FLo.op != Asse_MOV); in getRegUsage_AMD64Instr()
1722 vassert(mode64 == True); in mapRegs_AMD64Instr()
1958 vassert(offsetB >= 0); in genSpill_AMD64()
1959 vassert(!hregIsVirtual(rreg)); in genSpill_AMD64()
1960 vassert(mode64 == True); in genSpill_AMD64()
1980 vassert(offsetB >= 0); in genReload_AMD64()
1981 vassert(!hregIsVirtual(rreg)); in genReload_AMD64()
1982 vassert(mode64 == True); in genReload_AMD64()
2005 vassert(hregClass(r) == HRcInt64); in iregEnc210()
2006 vassert(!hregIsVirtual(r)); in iregEnc210()
2008 vassert(n <= 15); in iregEnc210()
2016 vassert(hregClass(r) == HRcInt64); in iregEnc3()
2017 vassert(!hregIsVirtual(r)); in iregEnc3()
2019 vassert(n <= 15); in iregEnc3()
2027 vassert(hregClass(r) == HRcInt64); in iregEnc3210()
2028 vassert(!hregIsVirtual(r)); in iregEnc3210()
2030 vassert(n <= 15); in iregEnc3210()
2038 vassert(hregClass(r) == HRcVec128); in vregEnc3210()
2039 vassert(!hregIsVirtual(r)); in vregEnc3210()
2041 vassert(n <= 15); in vregEnc3210()
2047 vassert(mod < 4); in mkModRegRM()
2048 vassert((reg|regmem) < 8); in mkModRegRM()
2054 vassert(shift < 4); in mkSIB()
2055 vassert((regindex|regbase) < 8); in mkSIB()
2202 vassert(gregEnc3210 < 16); in doAMode_M_enc()
2222 vassert(gregEnc3210 < 16); in doAMode_R_enc_reg()
2228 vassert(eregEnc3210 < 16); in doAMode_R_reg_enc()
2234 vassert( (gregEnc3210|eregEnc3210) < 16); in doAMode_R_enc_enc()
2264 vassert(0); in rexAMode_M__wrk()
2275 vassert(gregEnc3210 < 16); in rexAMode_M_enc()
2297 vassert(gregEnc3210 < 16); in rexAMode_R_enc_reg()
2303 vassert(eregEnc3210 < 16); in rexAMode_R_reg_enc()
2309 vassert((gregEnc3210|eregEnc3210) < 16); in rexAMode_R_enc_enc()
2398 vassert(n >= 0 && n <= 7); in do_ffree_st()
2425 vassert(nbuf >= 64); in emit_AMD64Instr()
2426 vassert(mode64 == True); in emit_AMD64Instr()
2908 vassert(0); // should never get here in emit_AMD64Instr()
2922 vassert(delta >= 0 && delta < 100/*arbitrary*/); in emit_AMD64Instr()
2927 vassert(delta >= 0 && delta < 100/*arbitrary*/); in emit_AMD64Instr()
2939 vassert(disp_cp_chain_me_to_slowEP != NULL); in emit_AMD64Instr()
2940 vassert(disp_cp_chain_me_to_fastEP != NULL); in emit_AMD64Instr()
2997 vassert(delta > 0 && delta < 40); in emit_AMD64Instr()
3010 vassert(disp_cp_xindir != NULL); in emit_AMD64Instr()
3052 vassert(delta > 0 && delta < 40); in emit_AMD64Instr()
3101 vassert(trcval != 0); in emit_AMD64Instr()
3116 vassert(delta > 0 && delta < 40); in emit_AMD64Instr()
3123 vassert(i->Ain.CMov64.cond != Acc_ALWAYS); in emit_AMD64Instr()
3131 vassert(i->Ain.CLoad.cond != Acc_ALWAYS); in emit_AMD64Instr()
3134 vassert(i->Ain.CLoad.szB == 4 || i->Ain.CLoad.szB == 8); in emit_AMD64Instr()
3154 vassert(delta > 0 && delta < 40); in emit_AMD64Instr()
3162 vassert(i->Ain.CStore.cond != Acc_ALWAYS); in emit_AMD64Instr()
3165 vassert(i->Ain.CStore.szB == 4 || i->Ain.CStore.szB == 8); in emit_AMD64Instr()
3183 vassert(delta > 0 && delta < 40); in emit_AMD64Instr()
3244 vassert(reg < 16); in emit_AMD64Instr()
3311 vassert(i->Ain.A87Free.nregs > 0 && i->Ain.A87Free.nregs <= 7); in emit_AMD64Instr()
3318 vassert(i->Ain.A87PushPop.szB == 8 || i->Ain.A87PushPop.szB == 4); in emit_AMD64Instr()
3426 vassert(i->Ain.SseUComIS.sz == 4); in emit_AMD64Instr()
3486 vassert(0); in emit_AMD64Instr()
3498 vassert(i->Ain.SseCStore.cond != Acc_ALWAYS); in emit_AMD64Instr()
3519 vassert(delta > 0 && delta < 40); in emit_AMD64Instr()
3525 vassert(i->Ain.SseCLoad.cond != Acc_ALWAYS); in emit_AMD64Instr()
3546 vassert(delta > 0 && delta < 40); in emit_AMD64Instr()
3552 vassert(i->Ain.SseLdzLO.sz == 4 || i->Ain.SseLdzLO.sz == 8); in emit_AMD64Instr()
3811 vassert(p - p0 == 3); in emit_AMD64Instr()
3815 vassert(p - p0 == 5); in emit_AMD64Instr()
3824 vassert(p - p0 == 8); /* also ensures that 0x03 offset above is ok */ in emit_AMD64Instr()
3826 vassert(evCheckSzB_AMD64() == 8); in emit_AMD64Instr()
3844 vassert(!(*is_profInc)); in emit_AMD64Instr()
3859 vassert(p - &buf[0] <= 64); in emit_AMD64Instr()
3880 vassert(endness_host == VexEndnessLE); in chainXDirect_AMD64()
3890 vassert(p[0] == 0x49); in chainXDirect_AMD64()
3891 vassert(p[1] == 0xBB); in chainXDirect_AMD64()
3892 vassert(read_misaligned_ULong_LE(&p[2]) == (Addr)disp_cp_chain_me_EXPECTED); in chainXDirect_AMD64()
3893 vassert(p[10] == 0x41); in chainXDirect_AMD64()
3894 vassert(p[11] == 0xFF); in chainXDirect_AMD64()
3895 vassert(p[12] == 0xD3); in chainXDirect_AMD64()
3948 vassert(delta == 0LL || delta == -1LL); in chainXDirect_AMD64()
3966 vassert(endness_host == VexEndnessLE); in unchainXDirect_AMD64()
4007 vassert(valid); in unchainXDirect_AMD64()
4033 vassert(endness_host == VexEndnessLE); in patchProfInc_AMD64()
4034 vassert(sizeof(ULong*) == 8); in patchProfInc_AMD64()
4036 vassert(p[0] == 0x49); in patchProfInc_AMD64()
4037 vassert(p[1] == 0xBB); in patchProfInc_AMD64()
4038 vassert(p[2] == 0x00); in patchProfInc_AMD64()
4039 vassert(p[3] == 0x00); in patchProfInc_AMD64()
4040 vassert(p[4] == 0x00); in patchProfInc_AMD64()
4041 vassert(p[5] == 0x00); in patchProfInc_AMD64()
4042 vassert(p[6] == 0x00); in patchProfInc_AMD64()
4043 vassert(p[7] == 0x00); in patchProfInc_AMD64()
4044 vassert(p[8] == 0x00); in patchProfInc_AMD64()
4045 vassert(p[9] == 0x00); in patchProfInc_AMD64()
4046 vassert(p[10] == 0x49); in patchProfInc_AMD64()
4047 vassert(p[11] == 0xFF); in patchProfInc_AMD64()
4048 vassert(p[12] == 0x03); in patchProfInc_AMD64()